Patents by Inventor Cory Wajda
Cory Wajda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170317022Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.Type: ApplicationFiled: July 17, 2017Publication date: November 2, 2017Inventors: Kai-Hung Yu, Gerrit J. Leusink, Cory Wajda, Tadahiro Ishizaka, Takahiro Hakamata
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Publication number: 20170241014Abstract: A method for material deposition is described in several embodiments. According to one embodiment, the method includes providing a substrate defining features to receive a deposition of material, initiating a flow of a Ru carbonyl precursor to the substrate, the Ru carbonyl precursor decomposing within the defined features such that a Ru metal film is deposited on surfaces of the defined features and CO gas is released, and stopping the flow of the Ru carbonyl precursor to the substrate. The method further includes flowing additional CO gas to the substrate after stopping the flow of the Ru carbonyl precursor to the substrate, and repeatedly cycling between process steps of flowing the Ru carbonyl precursor to the substrate and flowing the additional CO gas to the substrate. In one embodiment, the Ru carbonyl precursor contains Ru3(CO)12.Type: ApplicationFiled: February 17, 2017Publication date: August 24, 2017Inventors: Kai-Hung Yu, Gerrit J. Leusink, Cory Wajda, Tadahiro Ishizaka, Takahiro Hakamata
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Publication number: 20170236752Abstract: Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.Type: ApplicationFiled: February 9, 2017Publication date: August 17, 2017Inventors: Kai-Hung L. Yu, Manabu Oie, Kaoru Maekawa, Cory Wajda, Gerrit J. Leusink, Yuuki Kikuchi, Hiroaki Kawasaki, Hiroyuki Nagai
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Patent number: 9711449Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.Type: GrantFiled: June 3, 2016Date of Patent: July 18, 2017Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, Gerrit J. Leusink, Cory Wajda, Tadahiro Ishizaka, Takahiro Hakamata
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Publication number: 20170125517Abstract: Embodiments of the invention describe a method of corner rounding and trimming of nanowires used in semiconductor devices. According to one embodiment, the method includes providing in a process chamber a plurality of nanowires separated from each other by a void, where the plurality of nanowires have a height and at least substantially right angle corners, forming an oxidized surface layer on the plurality of nanowires using an oxidizing microwave plasma, removing the oxidized surface layer to trim the height and round the corners of the plurality of nanowires, and repeating the forming and removing at least once until the plurality of nanowires have a desired trimmed height and rounded corners.Type: ApplicationFiled: November 3, 2016Publication date: May 4, 2017Inventors: Kandabara N. Tapily, Ying Trickett, Chihiro Tamura, Cory Wajda, Gerrit J. Leusink, Kaoru Maekawa
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Patent number: 9607888Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.Type: GrantFiled: February 3, 2015Date of Patent: March 28, 2017Assignee: Tokyo Electron LimitedInventors: Kai-Hung Yu, Toshio Hasegawa, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven Consiglio, Cory Wajda, Kaoru Maekawa, Gert J. Leusink
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Publication number: 20170084464Abstract: A germanium-containing semiconductor device and a method for forming a germanium-containing semiconductor device are described. The method includes providing a germanium-containing substrate, depositing an aluminum-containing diffusion barrier layer on the germanium-containing substrate, depositing a high-k layer on the aluminum-containing diffusion barrier layer, and exposing the high-k layer to atomic oxygen to reduce the equivalent oxide thickness (EOT) of the high-k layer while avoiding oxidizing the germanium-containing substrate. The germanium-containing semiconductor device includes a germanium-containing substrate, an aluminum-containing diffusion barrier layer on the germanium-containing substrate, and a high-k layer on the aluminum-containing diffusion barrier layer, where the high-k layer has been exposed to atomic oxygen to reduce the EOT of the high-k layer while avoiding oxidizing the germanium-containing substrate.Type: ApplicationFiled: September 16, 2016Publication date: March 23, 2017Inventors: Kandabara N. Tapily, Robert D. Clark, Steven P. Consiglio, Cory Wajda, Gerrit J. Leusink
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Publication number: 20160358815Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.Type: ApplicationFiled: June 3, 2016Publication date: December 8, 2016Inventors: Kai-Hung Yu, Gerrit J. Leusink, Cory Wajda, Tadahiro Ishizaka, Takahiro Hakamata
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Publication number: 20150255267Abstract: Embodiments of the invention describe methods for forming a semiconductor device. According to one embodiment, the method includes depositing an aluminum-doped high-k film on a substrate by atomic layer deposition (ALD) that includes: a) pulsing a metal-containing precursor gas into a process chamber containing the substrate, b) pulsing an aluminum-containing precursor gas into the process chamber, where a) and b) are sequentially performed without an intervening oxidation step, and c) pulsing an oxygen-containing gas into the process chamber. The method can further include heat-treating the aluminum-doped high-k film to crystallize or increase the crystallization of the film.Type: ApplicationFiled: March 9, 2015Publication date: September 10, 2015Inventors: Kandabara N. Tapily, Robert D. Clark, Steven P. Consiglio, Cory Wajda, Gerrit J. Leusink
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Publication number: 20150221550Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.Type: ApplicationFiled: February 3, 2015Publication date: August 6, 2015Inventors: Kai-Hung Yu, Toshio Hasegawa, Tadahiro Ishizaka, Manabu Oie, Fumitaka Amano, Steven Consiglio, Cory Wajda, Kaoru Maekawa, Gert J. Leusink
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Patent number: 8722548Abstract: In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.Type: GrantFiled: September 24, 2010Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Shintaro Aoyama, Robert D. Clark, Steven P. Consiglio, Marinus Hopstaken, Hemanth Jagannathan, Paul Charles Jamison, Gert Leusink, Barry Paul Linder, Vijay Narayanan, Cory Wajda
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Patent number: 8460945Abstract: A method and system are provided for monitoring status of a system component in a process chamber of a batch type processing system. The method includes exposing a system component to light from a light source and monitoring interaction of the light with the system component to determine status of the system component. The method can detect light transmission and/or light reflection from a system component during a process that can include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, and a liner, and can further contain a protective coating.Type: GrantFiled: September 30, 2003Date of Patent: June 11, 2013Assignee: Tokyo Electron LimitedInventors: David L. O'Meara, Daniel Craig Burdett, Stephen H. Cabral, Gert Leusink, John William Kostenko, Cory Wajda
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Publication number: 20120074533Abstract: In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Applicants: Tokyo Electron (TEL)Limited, International Business Machines CorporationInventors: Shintaro Aoyama, Robert D. Clark, Steven P. Consiglio, Marinus Hopstaken, Hemanth Jagannathan, Paul Charles Jamison, Gert Leusink, Barry Paul Linder, Vijay Narayanan, Cory Wajda
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Publication number: 20110220148Abstract: A method for performing preventative maintenance in a substrate processing system is described. The method includes diagnosing a level of contamination in a substrate processing system, scheduling a wet clean process when necessary, and scheduling a dry clean process when necessary. The dry clean process may include an ozone cleaning process.Type: ApplicationFiled: March 12, 2010Publication date: September 15, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Steven P. CONSIGLIO, Cory WAJDA, Robert D. CLARK
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Patent number: 7964515Abstract: A method is provided for forming high dielectric constant (high-k) films for semiconductor devices. According to one embodiment, a metal-carbon-oxygen high-k film is deposited by alternately and sequentially exposing a substrate to a metal-carbon precursor and near saturation exposure level of an oxidation source containing ozone. The method is capable of forming a metal-carbon-oxygen high-k film with good thickness uniformity while impeding growth of an interface layer between the metal-carbon-oxygen high-k film and the substrate. According to one embodiment, the metal-carbon-oxygen high-k film may be treated with an oxidation process to remove carbon from the film.Type: GrantFiled: December 21, 2007Date of Patent: June 21, 2011Assignee: Tokyo Electron LimitedInventors: Robert D. Clark, Cory Wajda
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Publication number: 20110065287Abstract: A method is provided for forming a metal-silicon-containing film on a substrate by pulsed chemical vapor deposition. The method includes providing the substrate in a process chamber, maintaining the substrate at a temperature suited for chemical vapor deposition of a metal-silicon-containing film by thermal decomposition of a metal-containing gas and a silicon-containing gas on the substrate, exposing the substrate to a continuous flow of the metal-containing gas, and during the continuous flow, exposing the substrate to sequential pulses of the silicon-containing gas.Type: ApplicationFiled: September 11, 2009Publication date: March 17, 2011Applicant: TOKYO ELECTRON LIMITEDInventor: Cory Wajda
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Publication number: 20090163012Abstract: A method is provided for forming high dielectric constant (high-k) films for semiconductor devices. According to one embodiment, a metal-carbon-oxygen high-k film is deposited by alternately and sequentially exposing a substrate to a metal-carbon precursor and near saturation exposure level of an oxidation source containing ozone. The method is capable of forming a metal-carbon-oxygen high-k film with good thickness uniformity while impeding growth of an interface layer between the metal-carbon-oxygen high-k film and the substrate. According to one embodiment, the metal-carbon-oxygen high-k film may be treated with an oxidation process to remove carbon from the film.Type: ApplicationFiled: December 21, 2007Publication date: June 25, 2009Applicant: TOKYO ELECTRON LIMITEDInventors: Robert D. CLARK, Cory WAJDA
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Patent number: 7501352Abstract: The present invention generally provides a method for preparing an oxynitride film on a substrate. A surface of the substrate is exposed to oxygen radicals formed by ultraviolet (UV) radiation induced dissociation of a first process gas comprising at least one molecular composition comprising oxygen to form an oxide film on the surface. The oxide film is exposed to nitrogen radicals formed by plasma induced dissociation of a second process gas comprising at least one molecular composition comprising nitrogen using plasma based on microwave irradiation via a plane antenna member having a plurality of slits to nitridate the oxide film and form the oxynitride film.Type: GrantFiled: March 30, 2005Date of Patent: March 10, 2009Assignees: Tokyo Electron, Ltd., International Business Machines Corporation (“IBM”)Inventors: Masanobu Igeta, Cory Wajda, David L. O'Meara, Kristen Scheer, Toshihara Eurakawa
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Patent number: 7479454Abstract: A method and system for monitoring status of a system component during a process. The method includes exposing a system component to a reactant gas during a process, where the reactant gas is capable of etching the system component material to form an erosion product, and monitoring release of the erosion product during the process to determine status of the system component. Processes that can be monitored include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, an injector, a substrate holder, a liner, a pedestal, a cap cover, an electrode, and a heater, any of which can further include a protective coating.Type: GrantFiled: September 30, 2003Date of Patent: January 20, 2009Assignee: Tokyo Electron LimitedInventors: David L. O'Meara, Daniel Craig Burdett, Stephen H. Cabral, Gert Leusink, John William Kostenko, Cory Wajda
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Patent number: 7470591Abstract: A method is provided for reducing the metal content and controlling the metal depth profile of a gate dielectric layer in a gate stack. The method includes providing a substrate in a process chamber, depositing a gate dielectric layer on the substrate, where the gate dielectric layer includes a metal element. The metal element is selectively etched from at least a portion of the gate dielectric layer to form an etched gate dielectric layer with reduced metal content, and a gate electrode layer is formed on the etched gate dielectric layer.Type: GrantFiled: September 30, 2005Date of Patent: December 30, 2008Assignee: Tokyo Electron LimitedInventors: David L. O'Meara, YoungJong Lee, Cory Wajda