Abstract: A CAM memory cell including: a latch including N first TFETs serially connected one to the other between two supply electric potentials such that each source and drain of each first TFETs is connected either to one supply electric potentials or to the source or drain of another first TFETs, and wherein one electric potentials is applied on the gate of each first TFETs which are in reverse bias VDS and forward bias VGS, with N?2; an output block connected to N?1 storage nodes formed at connection points between the first TFETs, and configured to read a data stored in the storage nodes and/or to output a value representative of a matching or mismatching between a search data and the stored data; a write block configured to apply a data to be stored in the storage nodes.

Abstract: Tri-state inverter includes a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter, and a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero, wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.

Abstract: Memory latch comprising: a TFET; a capacitor; a storage node formed by the connection of a first terminal of the capacitor to a first electrode of the TFET; a control circuit configured to supply a first electric potential on a second terminal of the capacitor, a second electric potential on the gate of the TFET and a third electric potential on a second electrode of the TFET, such that: when the stored potential is low, the TFET is reverse biased with a conduction current obtained by band-to-band tunneling with a value higher than a capacitor leakage current; when the stored potential is high, the TFET is reverse biased with an OFF state current value less than the capacitor leakage current.

Abstract: A SRAM memory bit cell is provided that includes a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); and a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains). The control circuit is configured to provide, during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p TFET. The control circuit is further configured to provide, during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.

Abstract: Tri-state inverter comprising: a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter; a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero; and wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.

Abstract: SRAM memory bit cell comprising: a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains); wherein the control circuit is configured to provide: during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p-TFET; during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.

Abstract: Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on the value of the stored bit, and such that: the gate of the MOS transistor is connected to the memory point, and the gate of the TFET transistor is able to receive a read command signal; a first electrode of the MOS transistor is connected to the power supply terminal; a second electrode of the MOS transistor is connected to a first electrode of the TFET transistor; a second electrode of the TFET transistor is connected to the read bit line.

Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.

Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.

Abstract: Memory cell of the SRAM type, including storage transistors forming a memory point for storing a bit and a read port having at least one MOS transistor, a TFET transistor, a power terminal and a read bit line whereof a potential is designed to vary depending on value of the stored bit, and such that: the gate of the MOS transistor is connected to the memory point, and the gate of the TFET transistor is able to receive a read command signal; a first electrode of the MOS transistor is connected to the power supply terminal; a second electrode of the MOS transistor is connected to a first electrode of the TFET transistor; a second electrode of the TFET transistor is connected to the read bit line.

Abstract: A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region.

Abstract: A TFET transistor includes an intrinsic channel, source and drain extension regions, source and drain conductive regions, a gate surmounting the channel and laid out such that an end of the channel is not covered by the gate. The transistor includes a first arrangement for forming an isolating space between the sides of the gate and the source conductive region including a first and a second dielectric spacer. The extension region has a thickness strictly greater than that of the channel such that the extension region has an increased thickness opposite the gate dielectric layer. The first face of the first spacer is in contact with the side of the gate followed by the side of the gate dielectric layer such that the first face covers the whole of the side of the layer.

Abstract: A tunnel effect transistor includes a channel made of an intrinsic semiconductor material; source and drain extension regions on either side of the channel, the source extension region being made of a semiconductor material doped according to a first type of doping P or N and the drain extension region being made of a semiconductor material doped according to a second type of doping opposite to said first type of doping; source and drain conductive regions respectively in contact with the source and drain extension regions; a gate structure including a gate dielectric layer in contact with the channel and a gate area arranged such that the gate dielectric layer is arranged between the gate area and the channel; and an area doped according to the first type of doping inserted between the channel and the drain extension region.

Abstract: A TFET transistor includes an intrinsic channel, source and drain extension regions, source and drain conductive regions, a gate surmounting the channel and laid out such that an end of the channel is not covered by the gate. The transistor includes a first arrangement for forming an isolating space between the sides of the gate and the source conductive region including a first and a second dielectric spacer. The extension region has a thickness strictly greater than that of the channel such that the extension region has an increased thickness opposite the gate dielectric layer. The first face of the first spacer is in contact with the side of the gate followed by the side of the gate dielectric layer such that the first face covers the whole of the side of the layer.