CAM MEMORY CELL

Abstract

A CAM memory cell including: a latch including N first TFETs serially connected one to the other between two supply electric potentials such that each source and drain of each first TFETs is connected either to one supply electric potentials or to the source or drain of another first TFETs, and wherein one electric potentials is applied on the gate of each first TFETs which are in reverse bias VDS and forward bias VGS, with N≥2; an output block connected to N−1 storage nodes formed at connection points between the first TFETs, and configured to read a data stored in the storage nodes and/or to output a value representative of a matching or mismatching between a search data and the stored data; a write block configured to apply a data to be stored in the storage nodes.

Description

TECHNICAL FIELD AND PRIOR ART

The invention concerns the field of CAM (Content-Addressable Memory) memory cell, and advantageously a TFET 7T-TCAM (Ternary CAM).

Conventional 16T TCAM cells are expensive in terms of area and power consumption. The emergence of the IoT market pushes the development of more compact and energy efficient memory solutions.

The increasing demand for longer battery life time and, implicitly, for energy efficient devices, drives the research in the field of low power design in particular for the Internet of Things (IoT) era. Content addressable memory is a special type of memory which is accessed by data in place of physical location. This is an attractive feature which makes CAMs popular in high speed hardware based search implementations, such as look-up tables, data compression, image processing, network routers, etc. Speed of search in CAM comes at the cost of high power consumption. Efforts were made to optimize power consumption at both system and circuit level using various circuit techniques, like dynamic voltage frequency scaling, power gating, etc. and/or sacrificing bit cell area to provide less leakage while maintaining sufficient performance.

Binary CAM is the simplest type of CAM which uses data search words consisting entirely of 1s and 0s. Ternary CAM (TCAM) allows a third matching state of “X” or “don't care” for one or more bits in the stored data word, thus adding flexibility to the search.

Tunnel Field-Effect Transistors (TFETs) are better in terms of leakage because of different than CMOS in working principle. TFETs operate by band-to-band tunneling and, therefore, the theoretical subthreshold slope (S) is not limited to 60 mV/dec as in the CMOS case. It should be noted that fabricated TFETs with S as low as 30 mV/dec have already been measured. While a large variety of TFETs is present in the literature, a world performance record was established when integrated with FDSOI technology. Progress on TFET devices has encouraged research on TFET circuits and the few published reports on TFET circuits mostly focus on the design of TFET SRAM cells. Most of the reports on TFET SRAMs revealed difficulties in obtaining sufficient stability in read and write operations. As the stability in both operation modes is inherently low due to the electrical performance of TFETs and the low supply voltage, it is difficult for circuit designers to find the best balance between read and write. Due to lower than MOSFET ON current of TFETs and lower supply voltages, the performance of the TFET SRAMs is limited and cannot match the CMOS SRAM performance. In the document N. Gupta et al., «Ultra-Low Leakage Sub-32 nm TFET/CMOS Hybrid 32kb Pseudo Dual-Port Scratchpad with GHz Speed for Embedded Applications», in ISCAS, IEEE, 2015, 8T TFET Dual-Port SRAM is presented which overcomes the half-selection and write-disturb problems and provide lower than CMOS static power consumption (<5 fA/bit) even at 1V supply at the cost of increased bitcell area; performance is improved by using high supply voltages and dual ports.

In the document US 2011/0299326 A1, a 4T-TFET SRAM bit cell is proposed using negative differential resistance (NDR) property of TFETs in reverse bias. However, the architecture proposed in this document suffers from stability and performance issues. In order to maintain data during read operation, read current should be less than the hump current (in pA range) provided by NDR. Such constrain leads to an extremely slow read with the risk of data corruption while executing the operation. Moreover, the TFET transmission gate for data access limits the maximum operating voltage.

DESCRIPTION OF THE INVENTION

An aim of the invention is to propose an ultra-low standby power and compact CAM cell suitable for low voltage applications, and which requires less number, e.g. more than 50% reduction, of transistors in comparison to conventional CAM bit cells.

The invention proposes a CAM memory cell comprising at least:

• • a latch comprising N first TFETs serially connected one to the other between two supply electric potentials such that each of source and drain of each of the N first TFETs is connected either to one of the two supply electric potentials or to the source or the drain of another one of the N first TFETs, and wherein at least one of the two supply electric potentials is applied on the gate of each of the N first TFETs such that the N first TFETs are in reverse bias V_DS (that is V_DS≤0 for a n-TFET and V_DS≥0 for a p-TFET) and in forward bias V_GS (that is V_GS≥0 for a n-TFET and V_GS≤0 for a p-TFET), with N≥2;
  • an output block connected to (N−1) storage nodes formed at connection points between the N first TFETs, and able to read a data stored in the (N−1) storage nodes and/or to output a value representative of a matching or of a mismatching between a search data and the data stored in the (N−1) storage nodes;
  • a write block able to apply a data intended to be stored in the (N−1) storage nodes.

This cell takes advantage of the TFETs negative differential resistance (NDR) property to form the latch. This latch comprises N first TFETs and is able to store a data the value of which corresponding to one of N possible stable values which can be stored in the (N−1) storage nodes.

When the cell corresponds to a TCAM cell, the cell stores data in the ternary latch and avoids the use of a second latch to store mask bit.

An advantageous embodiment of the invention corresponds to TFET/CMOS hybrid TCAM cell.

The memory may be designed using Si-TFETs and MOSFETs which can be fabricated together in FDSOI CMOS process.

The CAM memory cell may be such that:

• • the write block comprises (N−1) MOSFETs and at least one first data line in which the data intended to be stored in at least one of the (N−1) storage nodes is able to be applied;
  • each one of the (N−1) MOSFETs has one of its source or drain connected to said at least one of the (N−1) storage nodes and the other one of its source or drain connected to the first data line.

In an advantageous embodiment, the write block may comprise (N−1) first data lines such that each one of the (N−1) first data line is connected to one of the (N−1) MOSFETs.

In this case, the gate of each of the (N−1) MOSFETs may be connected to a write word line in which a write control signal is able to be applied. This write control signal may control the triggering of a writing of data into the latch.

In a particular embodiment, the CAM memory cell may be such that:

• • the write block comprises at least two first data lines;
  • a first one of the (N−1) MOSFETs is a n-MOSFET having one of its source or drain connected to a first one of the two first data lines and the other one of its source or drain connected to a first one of the (N−1) storage nodes;
  • a second one of the (N−1) MOSFETs is a n-MOSFET having one of its source or drain connected to a second one of the two first data lines and the other one of its source or drain connected to a second one of the (N−1) storage nodes.

This particular embodiment may correspond to that of a TCAM.

The output block may comprise one or several second TFETs each having its gate connected to one of the (N−1) storage nodes, one of its source or drain connected to a match line and the other one of its source or drain connected to a second data line in which the search data is able to be applied, and wherein an electric potential of the match line is able to discharge when the search data does not correspond to the data stored in the (N−1) storage nodes. In this case, the output block is able to fulfill a search/lookup table function, which is able to compare a search data with the data stored in the latch and to output a value corresponding to the matching or the mismatching between the searched data and the stored data.

According to a particular embodiment, the CAM memory cell may be such that:

• • the output block comprises at least two second data lines;
  • a first one of the second TFETs is a n-TFET having its drain connected to the match line and its source connected to a first one of the two second data lines;
  • a second one of the second TFETs is a p-TFET having its source connected to the match line and its drain connected to a second one of the two second data lines;
  • the gates of said first one and second one of the second TFETs are connected to the same storage node or to two different storage nodes.

This particular embodiment may correspond to that of a TCAM.

In an advantageous embodiment, the first and second data lines may be the same data lines. However, in a variant embodiment, it is possible that the first data lines don't correspond to the second data lines.

In another configuration, the output block may comprise one or several second TFETs each having its gate connected to one of the (N−1) storage nodes, one of its source or drain connected to a read bit line and the other of its source or drain connected to a read word line in which a read triggering signal is intended to be applied, and wherein an electric potential of the read bit line is able to discharge or not according to the value stored in said one of the (N−1) storage nodes. In this configuration, the output block is able to read the value of the data stored in the latch and to output this stored value.

In a particular embodiment, N=3 and the CAM memory cell forms a TCAM.

The invention also concerns a CAM (or TCAM) memory array comprising several CAM memory cells as disclosed above, wherein the CAM memory cells are arranged according to an array of several rows and several columns.

BRIEF DESCRIPTION OF THE DRAWINGS

This invention will be understood easier in view of the examples of embodiments provided purely for indicative and non-limiting purposes, in reference to the appended drawings wherein:

FIG. 1 shows the characteristic I_D(V_DS) of a reverse biased n-TFET, for different values of V_GS;

FIGS. 2a-2c show symbolically the different behaviors of a reverse biased TFET;

FIG. 3 shows a CAM memory cell, subject-matter of the invention, according to a first embodiment;

FIG. 4 shows search data waveforms into the CAM memory cell shown on FIG. 3;

FIG. 5 shows write waveforms into the CAM memory cell shown on FIG. 3;

FIG. 6 shows schematically some parts of a CAM memory cell, subject-matter of the invention, according to a second embodiment;

FIG. 7 shows a second variant embodiment of an output block of a CAM memory cell, subject-matter of the invention;

FIG. 8 shows schematically the different blocks forming the CAM memory cell, subject-matter of the invention;

FIG. 9 shows an example of a TCAM memory array of TCAM memory cells, subject-matter of the invention.

Identical, similar or equivalent parts of the different figures described below have the same numeric references for the sake of clarity between figures.

The different parts shown in the figures are not necessarily drawn to scale, so as to make the figures more comprehensible.

The different possibilities (alternatives and embodiments) must not be understood to mutually exclude each other and can, thus, be combined with each other.

Detailed Description of Particular Embodiments

TFETs are reverse-biased p-i-n gated junctions that operate by tunneling effect, in which the electrostatic potential of the intrinsic region is controlled by a gate terminal. The TFETs used in the CAM memory bit cells described below may be calibrated and designed on data similar to that disclosed in the document C. ANGHEL et al., “30-nm Tunnel FET with improved performance and reduce ambipolar current”, IEEE Transactions on Electron Devices, 2011.

For example:

• • the TFETs are built using Low-k (SiO₂) spacers and a High-k (HfO₂) gate dielectric;
  • the gate and the spacers lengths are 30 nm each;
  • the gate dielectric physical thickness is 3 nm;
  • the silicon film thickness (tSi) used to form the source, drain and channel regions is 4 nm.

FIG. 1 shows the characteristic I_D(V_DS) (the absolute values of I_DS are shown in FIG. 1) of a reverse biased n-TFET, for different values of V_GS: V_GS=1 V for the curve 10, V_GS=0.75 V for the curve 12, V_GS=0.5 V for the curve 14 and V_GS=0.25 V for the curve 16. The p-TFET curves are similar except the V_DS is positive and V_GS negative. For this characteristic, three regions corresponding to three different behaviors of the TFET can be distinguished as follows:

• • region I, which is named the “hump”, wherein a conduction current I_Tunnel is obtained in the TFET by band-to-band tunneling (the charge injection mechanism corresponding to the band-to-band tunneling is symbolically shown in FIG. 2a);
  • region II, which is named the “flat-current region”, wherein the conduction current obtained in the region I is no longer obtained due to the non-overlapping bands (as shown symbolically in FIG. 2b);
  • region III, which is named the “p-i-n turn-on”, wherein the charge injection mechanism is dominated by the thermionic emission over the barrier, creating a current named I_Thermionic as shown symbolically in FIG. 2c. In this region III, the TFET has a behavior similar to a short-circuit.

For the region III, the reverse biased output characteristic is named “unidirectional” due to the fact that the gate loses the control over the TFET for high negative drain voltages.

The band-to-band tunneling current dominates the hump. The current severely reduces and attains its minimum in the flat current region, whereas the tunneling current is suppressed due to the non-overlapping bands. The turn-on of the p-i-n diode is dominated by the thermionic emission over the barrier.

FIG. 3 shows a 100 according to a first embodiment. In this first embodiment, the CAM memory cell 100 corresponds to a 7T-TCAM cell.

The cell 100 comprises three first TFETs 102.1, 102.2 and 102.3 serially connected one to the other and forming a latch 103. TFETs 102.1 and 102.2 are of the p type, and the TFET 102.3 is of the n type. The source of the p-TFET 102.1 is connected to the drain of the p-TFET 102.2, forming a first storage node 104.1. The electric potential in the first storage node 104.1 is named Q0. The sources of the p-TFET 102.2 is connected to the source of the n-TFET 102.3, forming a second storage node 104.2. The electric potential in the second storage node 104.2 is named Q1.

The first TFETs 102.1-102.3 are biased by a first supply electric potential VDD applied one the drain of the p-TFET 102.1 and a second supply electric potential forming a reference potential (ground) GND applied on the drain of the n-TFET 102.3. Thus, the first TFETs 102.1-102.3 are biased such that they are always in reverse bias V_DS range, i.e. V_DS≤0 for n-TFETs and V_DS≥0 for p-TFETs. In addition, GND is applied on the gates of the p-TFETs 102.1 and 102.2, and VDD is applied on the gate of the n-TFET 102.3, such that first TFETs 102.1-102.3 are in forward bias V_GS range, i.e. V_GS≤0 for p-TFETs and V_GS≥0 for n-TFETs.

Due to NDR property (see FIG. 1 region I), the first TFETs 102.1-102.3 maintain the V_DS=0 condition owing to the hump current near V_DS=0. This results in three valid storage combinations in the storage nodes 104.1 and 104.2, where {Q0Q1} can be {00}, {10} or {11}. For supply voltage VDD of 0.6V, {00} is maintained by TFETs 102.2 and 102.3 with both having V_DS=0 and TFET 102.1 having V_DS=0.6V, i.e. minimum current flow (see FIG. 1). Similarly {11} is maintained by TFETs 102.1 and 102.2 with V_DS=0 and TFET 102.3 with V_DS=−0.6V. {10} is maintained by TFETs 102.1 and 102.3 with V_DS=0 and TFET 102.2 with V_DS=0.6V. Value of {01} for {Q0Q1} is an unstable condition, i.e. forbidden state, with TFET 102.2 switched ON in forward V_DS condition.

The latch 103 formed by TFETs 102.1-102.3 can store ternary data using above mentioned three combinations of data. For example, ‘0’ is represented with {00} on {Q0Q1}, ‘1’ is represented by {11}, and ‘X’ or ‘don't care’ by {10}. However, it is possible to consider that the three valid storage combinations are associated differently to the values ‘0’, ‘1’ and ‘X’.

As shown in FIG. 3, TFET 102.2 is having hump current with V_GS=0 in order to make 0 and 1 stable at nodes 104.1 and 104.2, respectively. Another option, for TFETs where hump current is fully suppresses with V_GS=0, is to use either negative gate voltage on TFET 102.2 or add one more n-TFET device between nodes 104.1 and 104.2 with gate at VDD and V_DS negative.

The cell 100 also comprises an output block 106. In this first embodiment, the output block 106 is able to fulfill a search data function, that is outputting a signal which is representative of the matching or the mismatching between a search data and the data {Q0Q1} stored in the latch 103.

In this first embodiment, the output block 106 comprises a n-TFET 108.1 and a p-TFET 108.2, named second TFETs 108.1-108.2. The gate of the n-TFET 108.1 is connected to the second storage node 104.2, and the gate of the p-TFET 108.2 is connected to the first storage node 104.1. The drain of the n-TFET 108.1 and the source of the p-TFET 108.2 are connected to a match line ML. The source of the n-TFET 108.1 is connected to a data line DL providing the search data to the output block 106. The drain of the p-TFET 108.2 is connected to a complementary data line DLB providing the complemented value of the search data to the output block 106.

With this output block 106, the match line ML discharges only if either {Q0Q1} is {11} and search data is ‘0’ (i.e. DL=0 and DLB=VDD) or {Q0Q1}={00} and search data is ‘1’ (i.e. DL=VDD, DLB=0), i.e. mismatch condition. In case of match of data (matching between the searched data and the stored data), invalid search data ({01}) or don't care combinations {10} on {Q0Q1}, ML will remain precharged.

Read waveform is shown in FIG. 4. The curve referenced 20 corresponds to the value on DL and the curve references 22 (dotted line) corresponds to the value on DLB. The instant to represents the start of the search. In this example, the search value is ‘0’, which corresponds here to {00} stored in the latch 103. If {Q0Q1}={11}, the value on ML passes from ‘1’ (0.6V) to ‘0’ (0V) as shown by the curve 24. If a value other than {11} is searched, the value ML is ‘1’ before and after t0 (no discharging, as shown by the curve 26).

The cell 100 also comprises a write block 110 which is able to provide a data to be stored in the latch 103.

In this first embodiment, the write block 110 comprises a first n-MOSFET 112.1 and a second n-MOSFET 112.2. One of the source or drain of the first n-MOSFET 112.1 (the drain in FIG. 3) is connected to the first storage node 104.1, and one of the source or drain of the second n-MOSFET 112.2 (the source in FIG. 3) is connected to the second storage node 104.2. Write operation is done using write word line (WWL) connected to the gates of the n-MOSFETs 112.1 and 112.2 and data lines (DL connected to the source of the first n-MOSFET 112.1, and DLB connected to the drain of the second n-MOSFET 112.2. During a writing of data in the latch 103, the value {DL,DLB} can be {00}, {10} or {11}.

Since the drain current I_D of the first and second n-MOSFETs 112.1 and 112.2 is much higher than the current through the drain current through the TFETs 102.1-102.3 (i.e. hump current), it results in fast writing of data into storage nodes 104.1 and 104.2.

Write operation for different combination of values is shown in FIG. 5. Curve 30 corresponds to WWL signal, each pulse of this signal triggering a writing into the storage nodes 104.1 and 104.2. Curve 32 corresponds to DL and curve 34 (dotted line) corresponds to DLB. Curve 36 (dotted line) corresponds to the value stored into the first storage node 104.1, and curve 38 corresponds to the value stored into the second storage node 104.2.

Wordline boosting is used to overcome the limitation of using n-MOS for writing ‘1’ on storage nodes 104.1 and 104.2 ({Q0Q1}={11}).

In the first embodiment shown in FIG. 3, the data lines DL and DLB connected to the write block 110 are the same as those connected to the output block 106. However, it is possible that the data lines connected to the write block 110 are different than those connected to the output block 106.

In the first embodiment previously disclosed, the latch 103 of the cell 100 comprises three TFETs 102.1-102.3 forming two storage nodes 104.1, 104.2 able to store three possible combinations of values ({00}, {10} and {11}). More generally, the latch 103 of the cell comprises N TFETs 102.1-102.N forming N−1 storage nodes 104.1-104.(N−1) able to store N possible combinations of data, with N≥2. When N=2, the cell 100 corresponds to a binary CAM. When N=3, the cell 100 corresponds to a ternary CAM.

FIG. 6 schematically shows a latch 103 comprising N first TFETs 102.1-102.N forming N−1 storage nodes 104.1-104.(N−1) able to store N possible combinations of data. These N first TFETs 102.1-102.N are connected in series between two supplies VDD and GND. As shown on FIG. 6, the latch 103 comprises m n-TFET 102.1-102.m arranged on the side of GDD and (N−m) p-TFET 102.m+1-102.N arranged on the side of VDD. However all combinations of p-TFET and n-TFET are possible for the first TFETs 102 of the latch 103: all TFETs 102 corresponding to n-TFETs, all TFETs 102 corresponding to p-TFETs, or any combination of n-TFETs and p-TFETs.

All first TFETs 102.1-102.N of the latch 103 are in reverse bias V_DS and forward bias V_GS. Thus V_GS<0 and V_DS>0 for a p-TFET 102, and Thus V_GS>0 and V_DS<0 for a n-TFET 102.

Valid stable values on each storage node correspond to either VDD or GND.

Concerning the possible combinations of data, a stable combination of data is one fulfilling the following condition: V(104.1)≤V(104.2)≤ . . . ≤V(104.N−1).

Advantageously, the latch 103 can comprise eight TFETs 102.1-102.8 such that eight stable combinations of data can be stored in the seven storage nodes 104.1-104.7 formed by these TFETs 102.1-102.8. These eight stable combinations may correspond to the eight possible values of the 3-bits word. The table below represents these eight stable combinations of data:

104.7	0	1	1	1	1	1	1	1
104.6	0	0	1	1	1	1	1	1
104.5	0	0	0	1	1	1	1	1
104.4	0	0	0	0	1	1	1	1
104.3	0	0	0	0	0	1	1	1
104.2	0	0	0	0	0	0	1	1
104.1	0	0	0	0	0	0	0	1

In the first embodiment previously described, the output block 106 comprises elements able to fulfill a search data function, which may considered as corresponding to a lookup table function. As a first variant embodiment, it is possible that the output block 106 comprises elements forming a read port, which is able to output the value(s) stored in the latch 103, whatever this value. For example, the output block 106 can comprises one or several TFETs 114, each having its gate connected to one of the storage node(s) 104, its drain connected to a read bit line 116 (RBL) and its source connected to a read word line 118 (RWL). FIG. 6 represents such output block 106 for the reading of the N−1 storage nodes 104.1-104.N−1. The read word lines 118.1-118.N−1 may be used to select the row of an array of bit cells to be read. The signals on the read word lines 118 may be considered as read triggering signals. According to the value stored in the storage nodes 104.1-104.N−1, the read bit lines 116.1-116.N−1 can fully discharge or a single-ended sense amplifier (e.g. an inverter with skewed threshold voltage) can be used. For example, during a read operation, the value of the voltage applied on the read word line 118 is changed from a value corresponding to that of a stored bit ‘1’, equals to VDD, to a value corresponding to that of a stored bit ‘0’, e.g. 0V. If a value ‘0’ is stored in the storage 104, the value of the voltage on the read bit line 116 remains at a value corresponding to a ‘1’. If a value ‘1’ is stored in the storage node 104, the value of the voltage on the read bit line 116 goes to ‘0’.

According to a second variant embodiment, the search data function of the output block 106 may be fulfilled by TFETs such that, for one storage node 104, a n-TFET 120.1 and a p-TFET 120.2 have their gates connected to this storage node 104. FIG. 7 shows an example of output block 106 for the reading of one storage node 104, according to this second variant embodiment. The source of the n-TFET 120.1 is connected to the data line DL, and the drain of the n-TFET 120.1 is connected to the match line ML. The drain of the p-TFET 120.2 is connected to the data line DLB, and the source of the p-TFET 120.2 is connected to the match line ML.

The behavior of this output block 106 is close to that of the output block 106 previously disclosed on FIG. 3. According to the value of the searched data, which corresponds to the value applied on DL, the value on the match line ML is discharged or not according to a matching or not with the stored value in the storage node 104.

As for the output block 106, the write block 110 may comprise elements which are different than those previously disclosed in relation with the first embodiment of the FIG. 3.

FIG. 8 represents the different functional blocks of the CAM cell 100. The input data and control inputted into the write block 110 correspond to the value of the data intended to be stored in the latch 103 (e.g. values on DL and DLB in the first embodiment previously disclosed) and the control signal intended to trigger the writing operation into the latch 103 (e.g. value on WWL in the first embodiment previously disclosed). The output signal obtained at the output of the output block 106 corresponds to a value indicating a matching or a mismatching between a search value and the value stored in the latch 103 (e.g. value on ML in the previously disclosed first embodiment), and/or the value stored in the latch 103 (e.g. value on the read bit line 116 previously described). The control and/or search data inputted into the output block 106 correspond to the value of the searched data (e.g. values on DL and DLB in the previously disclosed first embodiment) and/or the value intended to trigger the reading operation of the stored data (e.g. value on the read word line 118 previously described).

An example CAM memory array 1000 is shown in FIG. 9. In this array, N×M CAM memory cells 100 are arranged according to an array of several rows and several columns. VDD, GND, DL and DLB are routed vertically such that the CAM cells 100 arranged in a same column are connected to the same column lines in which these signals are applied. WWL, ML are routed horizontally such that the memory devices 100 arranged in the same row are connected to the same row lines in which these signals are applied. In FIG. 9, four CAM memory devices 100.11, 100.1M, 100.N1 and 100.NM arranged in two different rows and two different columns are shown. In such CAM memory array 1000, bitcell area is optimized by reducing number of transistors and metal lines required per bit in comparison to conventional 16T-TCAM bitcell.

Generally, proposed cell 100 is ultra-low standby power and works for wide voltage range from 0.4V to 1V. Evaluated standby power is <2 fW/bit, which shows 3 decades improvement in comparison to state of the art low standby TCAMs. Less than 1 ns read and write time is achieved at 0.6V supply with match line load for 256 bit words.

More generally, the proposed cell 100 may be made with different TFET technology and fabrications. The values of the features of the TFETs may also be different.

Claims

1-11. (canceled)

12: A CAM memory cell comprising:

a latch comprising N first TFETs serially connected one to the other between two supply electric potentials such that each of source and drain of each of the N first TFETs is connected either to one of the two supply electric potentials or to the source or the drain of another one of the N first TFETs, and wherein at least one of the two supply electric potentials is applied on a gate of each of the N first TFETs such that the N first TFETs are in reverse bias VDS and in forward bias VGS, with N≥2;

an output block connected to N−1 storage nodes formed at connection points between the N first TFETs, and configured to read a data stored in the N−1 storage nodes and/or to output a value representative of a matching or of a mismatching between a search data and the data stored in the N−1 storage nodes;

a write block configured to apply a data to be stored in the N−1 storage nodes.

13: The CAM memory cell according to claim 12, wherein:

the write block comprises N−1 MOSFETs and at least one first data line in which the data to be stored in at least one of the N−1 storage nodes is able to be applied;

each one of the N−1 MOSFETs has one of its source or drain connected to the at least one of the N−1 storage nodes and the other one of its source or drain connected to the first data line.

14: The CAM memory cell according to claim 13, wherein the write block comprises N−1 first data lines such that each one of the N−1 first data line is connected to one of the N−1 MOSFETs.

15: The CAM memory cell according to claim 13, wherein the gate of each of the N−1 MOSFETs is connected to a write word line in which a write control signal is able to be applied.

16: The CAM memory cell according to claim 15, wherein:

the write block comprises at least two first data lines;

a first one of the N−1 MOSFETs is a n-MOSFET having one of its source or drain connected to a first one of the two first data lines and the other one of its source or drain connected to a first one of the N−1 storage nodes;

a second one of the N−1 MOSFETs is a n-MOSFET having one of its source or drain connected to a second one of the two first data lines and the other one of its source or drain connected to a second one of the N−1 storage nodes.

17: The CAM memory cell according to claim 12, wherein the output block comprises one or plural second TFETs each having its gate connected to one of the N−1 storage nodes, one of its source or drain connected to a match line and the other one of its source or drain connected to a second data line in which the search data is able to be applied, and wherein an electric potential of the match line is able to discharge when the search data does not correspond to the data stored in the N−1 storage nodes.

18: The CAM memory cell according to claim 17, wherein:

the output block comprises at least two second data lines;

a first one of the second TFETs is a n-TFET having its drain connected to the match line and its source connected to a first one of the two second data lines;

a second one of the second TFETs is a p-TFET having its source connected to the match line and its drain connected to a second one of the two second data lines;

the gates of the first one and second one of the second TFETs are connected to the same storage node or to two different storage nodes.

19: The CAM memory cell according to claim 12, wherein:

the write block comprises at least two first data lines;

the output block comprises at least two second data lines;

the first and second data lines are same data lines.

20: The CAM memory cell according to claim 12, wherein the output block comprises one or plural second TFETs each having its gate connected to one of the N−1 storage nodes, one of its source or drain connected to a read bit line and the other of its source or drain connected to a read word line in which a read triggering signal is to be applied, and wherein an electric potential of the read bit line is able to discharge or not according to the value stored in said one of the N−1 storage nodes.

21: The CAM memory cell according to claim 12, wherein N=3 and the CAM memory cell forms a TCAM.

22: CAM memory array comprising plural CAM memory cells according to claim 12, wherein the CAM memory cells are arranged according to an array of rows and columns.