Patents by Inventor Craig R. Frink
Craig R. Frink has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9166918Abstract: In some embodiments, an apparatus includes a transmission schedule module in at least one of a memory or a processing device that can select, at a first time, a data unit to send to a network device based at least in part on a value of a transmission rate counter indicating that the network is in a first state. The transmission schedule module can receive, at a second time, an indication of a number of buffers associated with the data unit and can calculate a size estimate of the data unit based on the number of buffers and a capacity associated with each buffer. The transmission schedule module can calculate at a third time, a temporary transmission rate count and can send a signal to transition the network device from the first state to a second state if the temporary transmission rate count meets a criterion.Type: GrantFiled: September 30, 2013Date of Patent: October 20, 2015Assignee: Juniper Networks, Inc.Inventors: Craig R. Frink, Gerald Lampert, Steven Aiken, Srihari R. Vegesna
-
Publication number: 20150236961Abstract: Stacked (i.e., hierarchically arranged) rate wheels schedule traffic flows in a network. A first rate wheel operates to efficiently schedule traffic flows in which traffic shaping parameters may be applied to individual traffic flows. A second rate wheel schedules group of the traffic flows in which traffic shaping parameters may be applied at the group level. In the context of an ATM network, the first rate wheel may operate at the virtual circuit level and the second rate wheel may operate at the virtual path level.Type: ApplicationFiled: April 30, 2015Publication date: August 20, 2015Inventor: Craig R. FRINK
-
Patent number: 9031079Abstract: Stacked (i.e., hierarchically arranged) rate wheels schedule traffic flows in a network. A first rate wheel operates to efficiently schedule traffic flows in which traffic shaping parameters may be applied to individual traffic flows. A second rate wheel schedules group of the traffic flows in which traffic shaping parameters may be applied at the group level. In the context of an ATM network, the first rate wheel may operate at the virtual circuit level and the second rate wheel may operate at the virtual path level.Type: GrantFiled: August 6, 2004Date of Patent: May 12, 2015Assignee: Juniper Networks, Inc.Inventor: Craig R. Frink
-
Patent number: 8107372Abstract: A system schedules traffic flows on an output port using a circular memory structure. The circular memory structure may be a rate wheel that includes a group of sequentially arranged slots. The rate wheel schedules the traffic flows in select ones of the slots based on traffic shaping parameters assigned to the flows. The rate wheel compensates for collisions between multiple flows that occur in the slots by subsequently skipping empty slots.Type: GrantFiled: October 27, 2008Date of Patent: January 31, 2012Assignee: Juniper Networks, Inc.Inventor: Craig R Frink
-
Patent number: 8098580Abstract: A system schedules traffic flows on an output port using circular memory structures. The circular memory structures may include rate wheels that include a group of sequentially arranged slots. The traffic flows may be assigned to different rate wheels on a per-priority basis.Type: GrantFiled: July 24, 2009Date of Patent: January 17, 2012Assignee: Juniper Networks, Inc.Inventor: Craig R. Frink
-
Publication number: 20090285231Abstract: A system schedules traffic flows on an output port using circular memory structures. The circular memory structures may include rate wheels that include a group of sequentially arranged slots. The traffic flows may be assigned to different rate wheels on a per-priority basis.Type: ApplicationFiled: July 24, 2009Publication date: November 19, 2009Applicant: JUNIPER NETWORKS, INC.Inventor: Craig R. FRINK
-
Patent number: 7583596Abstract: A system schedules traffic flows on an output port using circular memory structures. The circular memory structures may include rate wheels that include a group of sequentially arranged slots. The traffic flows may be assigned to different rate wheels on a per-priority basis.Type: GrantFiled: June 28, 2004Date of Patent: September 1, 2009Assignee: Juniper Networks, Inc.Inventor: Craig R. Frink
-
Patent number: 7457247Abstract: A system schedules traffic flows on an output port using a circular memory structure. The circular memory structure may be a rate wheel that includes a group of sequentially arranged slots. The rate wheel schedules the traffic flows in select ones of the slots based on traffic shaping parameters assigned to the flows. The rate wheel compensates for collisions between multiple flows that occur in the slots by subsequently skipping empty slots.Type: GrantFiled: June 28, 2004Date of Patent: November 25, 2008Assignee: Juniper Networks, Inc.Inventor: Craig R. Frink
-
Patent number: 7046251Abstract: A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality of sequences of HD digital images representing a frame or field of HD motion video data. The non-linear editor provides a configuration control signal to identify processing to be performed on the HD video data and defines a video program to be rendered using the stored HD digital images. An input serial digital interface and an output serial digital interface in the non-linear editor provide the HD video data to be edited. A multiformat video router controls the HD video data sent between the non-linear editor and the video processing equipment. The router is video interconnected to the video processing equipment and to the serial digital interfaces of the non-linear editor.Type: GrantFiled: February 27, 2003Date of Patent: May 16, 2006Assignee: Avid Technology, Inc.Inventors: Morton Tarr, Peter Fasciano, Craig R. Frink
-
Patent number: 6961801Abstract: Command data may be embedded in the data transmitted over an interconnect between video devices to specify memory addresses in a destination device. Using an embedded address allows address-dependent data to be transmitted over the interconnect without losing these attributes. For example, compressed video may be transferred from a disk controller to a memory device using this interconnection protocol without losing address attributes of the bus architecture. The address information may be used either to read data from or to write data to a device over the interconnect into randomly-accessible memory locations.Type: GrantFiled: April 3, 1998Date of Patent: November 1, 2005Assignee: Avid Technology, Inc.Inventor: Craig R. Frink
-
Patent number: 6678002Abstract: A system provides real-time previsualization of effects to be added to high definition (HD) video data and real-time rendering of the HD video data including the added effects. The computer based system for editing high definition television (HDTV) resolution video includes a high definition video system connected to a standard definition video system and a high definition storage system. A resizer reformats the high definition video data to standard definition resolution for real-time processing and previsualization.Type: GrantFiled: March 7, 2001Date of Patent: January 13, 2004Assignee: Avid Technology, Inc.Inventors: Craig R. Frink, Raymond Cacciatoro
-
Publication number: 20030133448Abstract: A packet-based protocol includes data flow control signals for efficient transmission of data on various interconnects, including high speed parallel and serial interconnects. The packet protocol also enables routing of data in large systems or across standard video and computing networks. The packet protocol is data independent and permits sharing of different types of video data over a common interconnect and system design. The packet protocol also offers a flexible method for routing data between devices. Command data also may be sent between devices using this protocol. Using this packet protocol, any data storage or data processing device also may operate as a switch and may implement data flow control over its input and output interconnects. Flow controlled data transfer may be implemented using this protocol in a manner that is independent of the transport medium of the interconnect.Type: ApplicationFiled: April 3, 1998Publication date: July 17, 2003Inventors: CRAIG R. FRINK, ANDREW V. HOAR
-
Publication number: 20030128301Abstract: A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality of sequences of HD digital images representing a frame or field of HD motion video data. The non-linear editor provides a configuration control signal to identify processing to be performed on the HD video data and defines a video program to be rendered using the stored HD digital images. An input serial digital interface and an output serial digital interface in the non-linear editor provide the HD video data to be edited. A multiformat video router controls the HD video data sent between the non-linear editor and the video processing equipment. The router is video interconnected to the video processing equipment and to the serial digital interfaces of the non-linear editor.Type: ApplicationFiled: February 27, 2003Publication date: July 10, 2003Inventors: Morton Tarr, Peter Fasciano, Craig R. Frink
-
Patent number: 6407775Abstract: Film frames, or other images in which fields are captured at the same point in time, may be processed as a sequence of temporally coherent image fields or as progressive images. Such images may be obtained, for example, by digitizing signals from a telecine and dropping redundant fields inserted by the telecine. These fields may be stored in a buffer. Two fields of a given frame are read from the buffer by a resizer in accordance with read instructions, which may be determined according to any specified pulldown sequence, an output image size, and resize instructions, such as pan and scan or letterbox instructions. The resizer also may be informed of the input image size if it is not presumed. Thus, the full input image from which an output image may be generated is used by the resizer to generate output image. The resizer uses data in the input image received at one rate to generate one output image at the output rate.Type: GrantFiled: April 16, 1999Date of Patent: June 18, 2002Assignee: Avid Technology, Inc.Inventors: Craig R. Frink, Raymond D. Cacciatore
-
Patent number: 6327253Abstract: Multiple data processing devices may be interconnected through a switching mechanism while simultaneously conveying flow control information over the interconnect. Mechanisms are provided to ensure that the flow of data to and from interconnected devices has completed prior to changing the configuration of the switch. The switch may be a circuit switch, such as a crossbar switch, or a packet switch or a memory. The switch may be a separate device or may be part of either an input section or an output section of a data processing device. The configuration of the switch may be defined by command data loaded from a central controller, host computer, or other device connected to the switch, such as a sending device or a receiving device with a full duplex connection to the switch. The loading of a new configuration in the switch may be controlled by command data from a sending device, receiving device, or host computer, or by a controller that is responsive to a boundary signal transmitted over the interconnect.Type: GrantFiled: April 3, 1998Date of Patent: December 4, 2001Assignee: Avid Technology, Inc.Inventor: Craig R. Frink
-
Patent number: 6304932Abstract: A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.Type: GrantFiled: October 25, 2000Date of Patent: October 16, 2001Assignee: Hewlett-Packard CompanyInventors: Michael L. Ziegler, Robert J. Brooks, William R. Bryg, Craig R. Frink, Thomas R. Hotchkiss, Robert D. Odineal, James B. Williams, John L. Wood
-
Publication number: 20010017667Abstract: A system provides real-time previsualization of effects to be added to high definition (HD) video data and real-time rendering of the HD video data including the added effects. The computer based system for editing high definition television (HDTV) resolution video includes a high definition video system connected to a standard definition video system and a high definition storage system. A resizer reformats the high definition video data to standard definition resolution for real-time processing and previsualization.Type: ApplicationFiled: March 7, 2001Publication date: August 30, 2001Inventors: Craig R. Frink, Raymond D. Cacciatore
-
Publication number: 20010009446Abstract: A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality of sequences of HD digital images representing a frame or field of HD motion video data. The non-linear editor provides a configuration control signal to identify processing to be performed on the HD video data and defines a video program to be rendered using the stored HD digital images. An input serial digital interface and an output serial digital interface in the non-linear editor provide the HD video data to be edited. A multiformat video router controls the HD video data sent between the non-linear editor and the video processing equipment. The router is video interconnected to the video processing equipment and to the serial digital interfaces of the non-linear editor.Type: ApplicationFiled: March 7, 2001Publication date: July 26, 2001Inventors: Morton Tarr, Peter Fasciano, Craig R. Frink
-
Patent number: 6239815Abstract: In order to efficiently use processing and transmission bandwidth and data storage of a computer system, video data is represented using integer and fractional values. The integer value has a precision defined by the precision of the data paths of the computer system. These integer and fractional components are packed into byte-oriented data packets in a manner that minimizes waste of storage space and transmission bandwidth. This packing of data also may be done in such a way so as to minimize processing for performing packing and unpacking of the data. Because the video data may be easily separated and combined into its integer and fractional components, these components may be processed or transported separately, in parallel or in series, and then later recombined. As a result, lower precision devices may be used in parallel to process or transport streams of higher precision data without having a high precision data processing or transport path.Type: GrantFiled: April 3, 1998Date of Patent: May 29, 2001Assignee: Avid Technology, Inc.Inventors: Craig R. Frink, Raymond D. Cacciatore, Hamed Eshraghian
-
Patent number: 6229576Abstract: A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality of sequences of HD digital images representing a frame or field of HD motion video data. The non-linear editor provides a configuration control signal to identify processing to be performed on the HD video data and defines a video program to be rendered using the stored HD digital images. An input serial digital interface and an output serial digital interface in the non-linear editor provide the HD video data to be edited. A multiformat video router controls the HD video data sent between the non-linear editor and the video processing equipment. The router is video interconnected to the video processing equipment and to the serial digital interfaces of the non-linear editor.Type: GrantFiled: April 3, 1998Date of Patent: May 8, 2001Assignee: Avid Technology, Inc.Inventors: Morton Tarr, Peter Fasciano, Craig R. Frink