Abstract: A system provides real-time previsualization of effects to be added to high definition (HD) video data and real-time rendering of the HD video data including the added effects. The computer based system for editing high definition television (HDTV) resolution video includes a high definition video system connected to a standard definition video system and a high definition storage system. A resizer reformats the high definition video data to standard definition resolution for real-time processing and previsualization.

Abstract: A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.

Abstract: An interface enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls the flow of data between the processing elements. The flow control allows the processing elements to be data independent, i.e., the processing elements need not be designed for a fixed sample rate or resolution, sample format, or other data dependent factors. When used with digital motion video data, the processing elements may process motion video data at various temporal and spatial resolutions and color formats and precisions. Flow of data between processing elements may be controlled by handshake signals indicating whether the data output by the sender is valid and whether the receiver can receive data. The sender transmits data and asserts a valid signal along with the data in response to a request signal from the receiver. The request signal may be asserted by the receiver and responded to asynchronously by the sender with the transmission of the data by the sender.

Abstract: A memory is used as a data buffer and switch between devices producing and consuming data in combination with a separate control channel which conveys flow control information between the devices connected through the memory. The control channel includes a signal sent from a sender to a receiver granting the receiver permission to read data from the memory. The receiver replies with a signal indicating that data has been read from the memory, permitting the sender to write data to the memory. The memory is considered a circular buffer by the sender. The sender writes data into the memory at sequential locations until the end of the circular buffer is reached. This end of the buffer may be represented by a limit pointer. When data is written to the memory, the sender indicates the amount of valid data in the memory in a signal to the receiver over the control channel. The receiver receives this signal and reads data from the memory up to and limited by the amount indicated by the sender.

Abstract: The present invention provides a generic interface which enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls flow of data between the processing elements. The flow control allows the processing elements to be data independent from, i.e., the processing elements need not be designed for a fixed sample rate or resolution, sample format and other data dependent factors. When used with digital motion video data, the processing elements may process motion video data at various temporal and spatial resolutions and color formats. Flow of data between processing elements may be controlled by handshake signals indicating whether the sender has valid data and the receiver can receive data. When valid data is available at the sender and is requested by the receiver, a transfer of data occurs. The characteristics of the data, and functions to be performed on the data may be specified using control inputs to the processing elements.

Abstract: A split transaction bus system that accommodates atomic operations without locking the bus and without the possibility of deadlock during the atomic operations. The bus system may be used in a computer system that includes a bus, component modules that send transactions to each other on the bus, and a bus controller that limits the types of transactions that can be sent on the bus at any given time. When one module is performing an atomic operation, the bus controller limits transactions to those that do not change the memory image that existed when the atomic operation was commenced. The bus controller, however, permits responses or returns of data, assuming the response or return does not alter the current value of data.

Abstract: A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.