Patents by Inventor Craig Robertson
Craig Robertson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11048643Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: March 3, 2020Date of Patent: June 29, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 11023387Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: February 5, 2020Date of Patent: June 1, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 11023386Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: February 5, 2020Date of Patent: June 1, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 11023315Abstract: Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.Type: GrantFiled: October 3, 2019Date of Patent: June 1, 2021Assignee: Radian Memory Systems, Inc.Inventors: Mike Jadon, Craig Robertson, Robert Lercari
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Patent number: 11003586Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: February 5, 2020Date of Patent: May 11, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 10994431Abstract: An ambulatory cutting device is provided. The ambulatory cutting device provides a blade mounted, by way of a blade holding assembly, to a wheeled frame. The wheeled frame has handles for a user to push the wheeled frame along a surface supporting a roofing membrane or other cuttable membrane, wherein the blade holding assembly maintains the mounted blade at an elevation just below the supporting surface so that the membrane is cut as a user pushes the wheeled frame.Type: GrantFiled: November 26, 2019Date of Patent: May 4, 2021Inventor: Roger Craig Robertson
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Patent number: 10977188Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: February 3, 2020Date of Patent: April 13, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 10956082Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.Type: GrantFiled: December 4, 2019Date of Patent: March 23, 2021Assignee: Radian Memory Systems, Inc.Inventors: Alan Chen, Craig Robertson, Robert Lercari, Andrey V. Kuzmin
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Patent number: 10915458Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: February 3, 2020Date of Patent: February 9, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Publication number: 20200171682Abstract: An ambulatory cutting device is provided. The ambulatory cutting device provides a blade mounted, by way of a blade holding assembly, to a wheeled frame. The wheeled frame has handles for a user to push the wheeled frame along a surface supporting a roofing membrane or other cuttable membrane, wherein the blade holding assembly maintains the mounted blade at an elevation just below the supporting surface so that the membrane is cut as a user pushes the wheeled frame.Type: ApplicationFiled: November 26, 2019Publication date: June 4, 2020Inventor: Roger Craig Robertson
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Patent number: 10642748Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: August 29, 2017Date of Patent: May 5, 2020Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 10560620Abstract: The present invention relates to portable image acquisition apparatus (10). The portable image acquisition apparatus (10) is configured to acquire at least one image of apart of a human or animal body. The portable image acquisition apparatus comprises a main body (12) defining a window (20) and an imaging arrangement (16) operable to acquire an image of a part of a human or animal body by way of an imaging path which passes through the window (20). The portable image acquisition apparatus (10) also comprises a lighting module (14) comprising a light source and an optical arrangement (50), the lighting module (14) and the main body (12) being configured to releasably couple with each other when in use. The light source is configured to emit a beam of non-coherent light in a direction substantially perpendicular to the imaging path.Type: GrantFiled: October 24, 2013Date of Patent: February 11, 2020Assignee: EPIPOLE LIMITEDInventor: Craig Robertson
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Patent number: 10552085Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.Type: GrantFiled: July 15, 2016Date of Patent: February 4, 2020Assignee: Radian Memory Systems, Inc.Inventors: Alan Chen, Craig Robertson, Robert Lercari, Andrey V. Kuzmin
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Patent number: 10552058Abstract: Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.Type: GrantFiled: July 15, 2016Date of Patent: February 4, 2020Assignee: Radian Memory Systems, Inc.Inventors: Mike Jadon, Craig Robertson, Robert Lercari
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Publication number: 20200022869Abstract: A package has a plurality of seamless compartments coupled together. A different one of the plurality compartments each includes a different respective one of a plurality of respective void spaces and a different respective one of a plurality of respective void space delimiting surfaces. A different one of a plurality of fill entries each forms a fluent entry into a different respective compartment's void space. At least one fill entry of said plurality is in an elastomeric portion of said package, and the at least one fill entry has a largest cross sectional area which is equal to or less than 25% of a largest cross sectional area of the compartment having the respective void space for which the fill entry forms the fluent entry. Each void space delimiting surface follows an outline of a separate 3D pill shape.Type: ApplicationFiled: September 15, 2019Publication date: January 23, 2020Inventor: Craig Robertson
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Publication number: 20190330954Abstract: The invention relates to a packer assembly comprising an inner packer element and an outer concentric packer element, an actuator which is slidable over the outer packer element to deflect the outer packer element inwards against the inner packer element and a sensor for detecting linear movement of the actuator relative to the outer packer element.Type: ApplicationFiled: February 20, 2017Publication date: October 31, 2019Applicant: Oil States Industries (UK) LimitedInventors: Richard JOHNSTON, Craig ROBERTSON, John GALLAGHER
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Patent number: 10456327Abstract: A package has a plurality of seamless compartments coupled together. A different one of the plurality compartments each includes a different respective one of a plurality of respective void spaces and a different respective one of a plurality of respective void space delimiting surfaces. A different one of a plurality of fill entries each forms a fluent entry into a different respective compartment's void space. At least one fill entry of said plurality is in an elastomeric portion of said package, and the at least one fill entry has a largest cross sectional area which is equal to or less than 25% of a largest cross sectional area of the compartment having the respective void space for which the fill entry forms the fluent entry. Each void space delimiting surface follows an outline of a separate 3D pill shape.Type: GrantFiled: August 18, 2016Date of Patent: October 29, 2019Inventor: Craig Robertson
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Patent number: 10437700Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.Type: GrantFiled: August 19, 2016Date of Patent: October 8, 2019Assignee: UltraSoC Technologies LimitedInventors: Iain Craig Robertson, Andrew Brian Thomas Hopkins, Michael Jonathan Thyer
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Publication number: 20190273631Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson
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Patent number: 10326612Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.Type: GrantFiled: August 24, 2016Date of Patent: June 18, 2019Assignee: UltraSoC Technologies LimitedInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson