Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.

Abstract: A tipping chair (10) includes a main strut (12),a pivot seat (34) on the main strut (12), a pivot slot (18) defined the main strut (12) and a pivot strut (24) pivotally secured within the pivot slot (18). Pivoting a prop end (28) of the pivot strut (24) out of the pivot slot (18) of the main strut (12) backward toward a bottom end (14)of the main strut (12) causes a seat end (26) of the pivot strut (24) to raise the pivot seat(34) , and the seat end (26) becomes secured to a latch (42) on a brace surface (40) opposed to a seating surface (38) of the pivot seat (34) to postion the chair (10) in a seated.configuration. Reversing the process returns the chair (10) to a flat, stored configuration to be optionally stored as wall art.

Abstract: Compositions for gypsum board are disclosed, comprising a mixture of a gypsum slurry and a pre-generated foam and a coalescing agent. The coalescing agent comprises one or more coalescing agents that are added to the composition singly, separately or in combination to change the size and distribution of the air bubbles in the foamed gypsum slurry. The resulting gypsum cores have increased nail pull resistance and an improved facer/gypsum core bond.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: The tipping chair (10) includes a main strut (12), a pivot seat (34) on the strut (12), a pivot slot (18) defined in the main strut (12) and a pivot strut (24) pivotally secured within the slot (18). Pivoting a prop end (28) of the pivot strut (24) out of the slot (18) of the main strut (12) backward toward a bottom end (14) of the main strut (12) causes a seat end (26) of the pivot strut (24) to raise the pivot seat (34), and the seat end (26) becomes secured to a latch (42) on an a brace surface (40) opposed to a seating surface (38) of the pivot seat (34) to position the chair (10) in a seated configuration. Reversing the process returns the chair (10) to a flat, stored configuration to be optionally stored as wall art.

Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.

Abstract: Hierarchical address virtualization within a memory controller and configurable block device allocation are disclosed. Respective virtual block devices (VBDs) are defined in flash memory managed by a common memory controller, with data access managed using address virtualization techniques. The common memory controller then tracks the need for maintenance operations independently for each VBD. Information may be received from the common memory controller regarding the need for maintenance operations in respective virtual block devices (VBDs), and commands are then selectively issued to the common memory controller in a manner so as to independently schedule these operations for the respective VBDs; performance of maintenance operations by the memory controller in a first VBD is unconstrained by performance characteristics associated with a second VBD.

Abstract: A package has a plurality of seamless compartments coupled together. A different one of the plurality compartments each includes a different respective one of a plurality of respective void spaces and a different respective one of a plurality of respective void space delimiting surfaces. A different one of a plurality of fill entries each forms a fluent entry into a different respective compartment's void space. At least one fill entry of said plurality is in an elastomeric portion of said package, and the at least one fill entry has a largest cross sectional area which is equal to or less than 25% of a largest cross sectional area of the compartment having the respective void space for which the fill entry forms the fluent entry. Each void space delimiting surface follows an outline of a separate 3D pill shape.

Abstract: A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link.

Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.

Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.

Abstract: This disclosure provides techniques of hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.

Abstract: Compositions for gypsum board are disclosed, comprising a mixture of a gypsum slurry and a pre-generated foam and a coalescing agent. The coalescing agent comprises one or more coalescing agents that are added to the composition singly, separately or in combination to change the size and distribution of the air bubbles in the foamed gypsum slurry. The resulting gypsum cores have increased nail pull resistance and an improved facer/gypsum core bond.

Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.

Abstract: An object based file system for storing and accessing objects is disclosed. The file system may be implemented as a method in hardware, firmware, software, or a combination thereof. The method may include receiving from an application program an object write request. A selected storage node on which to store the object may be selected, including identifying a least busy storage node and/or a least full storage node. The object and the object write request may be sent to the selected storage node. A write success message may be received from the selected storage node. The successful writing of the object may be reported to the application program.

Abstract: An object based file system for storing and accessing objects is disclosed. The file system may be implemented as a method in hardware, firmware, software, or a combination thereof. The method may include receiving from an application program an object write request. A selected storage node on which to store the object may be selected, including identifying a least busy storage node and/or a least full storage node. The object and the object write request may be sent to the selected storage node. A write success message may be received from the selected storage node. The successful writing of the object may be reported to the application program.

Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.

Abstract: The present invention relates to portable image acquisition apparatus (10). The portable image acquisition apparatus (10) is configured to acquire at least one image of apart of a human or animal body. The portable image acquisition apparatus comprises a main body (12) defining a window (20) and an imaging arrangement (16) operable to acquire an image of a part of a human or animal body by way of an imaging path which passes through the window (20). The portable image acquisition apparatus (10) also comprises a lighting module (14) comprising a light source and an optical arrangement (50), the lighting module (14) and the main body (12) being configured to releasably couple with each other when in use. The light source is configured to emit a beam of non-coherent light in a direction substantially perpendicular to the imaging path.

Abstract: An integrated circuit chip device comprising: system circuitry; debugging circuitry configured to debug the system circuitry, the debugging circuitry being segmented into zones; wherein the debugging circuitry comprises an interconnect fabric configured to route debug messages through a zone from a zone entry node of the interconnect fabric to a zone exit node of the interconnect fabric; and wherein the debugging circuitry is configured to, on receiving a debug message at a zone entry node that is shorter than a specified length, modify the debug message to form a modified debug message by increasing the length of the debug message to the specified length.