Patents by Inventor Craig T. Salling
Craig T. Salling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7256460Abstract: A protection circuit for protecting an integrated circuit pad 201 against an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor 202 (preferably pMOS) in a substrate 205 (preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground 203. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a component 221 determining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor 222 (for example about 40 to 60?) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion.Type: GrantFiled: November 30, 2004Date of Patent: August 14, 2007Assignee: Texas Instruments IncorporatedInventors: Craig T. Salling, Charvaka Duvvury, Gianluca Boselli
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Patent number: 7253464Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb.Type: GrantFiled: September 21, 2006Date of Patent: August 7, 2007Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 7236387Abstract: A ground potential is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A fraction of a programming voltage is applied to other word lines coupled to control gates of non-selected memory cells not associated with the first word line. The programming voltage is applied to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell. A fraction of the programming voltage is applied to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.Type: GrantFiled: May 17, 2005Date of Patent: June 26, 2007Assignee: Micron Technology, Inc.Inventor: Craig T. Salling
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Patent number: 7199413Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb.Type: GrantFiled: April 4, 2005Date of Patent: April 3, 2007Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 7123503Abstract: A programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell. A fraction of the programming voltage is applied to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line, and other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.Type: GrantFiled: May 17, 2005Date of Patent: October 17, 2006Assignee: Micron Technology, Inc.Inventor: Craig T. Salling
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Patent number: 7002198Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: GrantFiled: August 26, 2004Date of Patent: February 21, 2006Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 6982449Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: GrantFiled: August 26, 2004Date of Patent: January 3, 2006Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 6944043Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: GrantFiled: January 9, 2003Date of Patent: September 13, 2005Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 6937501Abstract: A programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell. A fraction of the programming voltage is applied to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line, and other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.Type: GrantFiled: October 6, 2003Date of Patent: August 30, 2005Assignee: Micron Technology, Inc.Inventor: Craig T. Salling
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Patent number: 6903960Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: GrantFiled: August 26, 2004Date of Patent: June 7, 2005Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 6900969Abstract: Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry (101) on a substrate (106) that discharges an ESD pulse to the integrated circuit to ground (104a). The protection circuitry (100) also includes a drive circuitry (102) that uses a portion of the ESD pulse voltage to bias the substrate (106) using a first guard ring (110) in the substrate (106), which surrounds the discharge circuitry (101) and drive circuitry (102). The protection circuitry (100) further includes a second guard ring (120) in substrate (106), which surrounds the first guard ring (110) and connects to Vss/ground potential (104c), thereby providing uniformity of the substrate bias.Type: GrantFiled: December 11, 2002Date of Patent: May 31, 2005Assignee: Texas Instruments IncorporatedInventors: Craig T. Salling, Roger A. Cline
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Patent number: 6888185Abstract: Depletion mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: GrantFiled: August 26, 2004Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 6888747Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: GrantFiled: July 26, 2004Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 6888738Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: GrantFiled: July 26, 2004Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 6882560Abstract: A first fraction of a programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to other word lines coupled to control gates of non-selected memory cells. The first fraction of the programming voltage is applied to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells. A second fraction of the programming voltage is applied to a first bit line coupled to a second source/drain region of the selected memory cell and to other bit lines coupled to second source/drain regions of non-selected memory cells.Type: GrantFiled: October 6, 2003Date of Patent: April 19, 2005Assignee: Micron Technology, Inc.Inventor: Craig T. Salling
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Patent number: 6875650Abstract: On the surface of a semiconductor material of a first conductivity type 101a, a lateral MOS transistor 100 is described surrounded by a well 171 of the opposite conductivity type and, nested within the well, an electrical isolation region 102. The semiconductor region 101a embedding this transistor has a resistivity higher than the remainder of the semiconductor material 101 and further contains a buried layer 160 of the opposite conductivity type. This layer 160 extends laterally to the wells 171, thereby electrically isolating the near-surface portion of the semiconductor region from the remainder of the semiconductor material, and enabling the MOS transistor to operate as an electrically isolated high-voltage I/O transistor for circuit noise reduction, while having low drain junction capacitance. In the first embodiment of the invention (FIG.Type: GrantFiled: October 14, 2003Date of Patent: April 5, 2005Assignee: Texas Instruments IncorporatedInventors: Craig T. Salling, Zhiqiang Wu
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Patent number: 6876022Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: GrantFiled: November 27, 2002Date of Patent: April 5, 2005Assignee: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber
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Patent number: 6858902Abstract: A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304), its source (304b) and its gate (304c) connected to ground potential and its drain (304a) connected to the I/O pad. A well of the opposite conductivity type, partially separated from the substrate by shallow trench isolations, has a diode (302), its anode (302b) connected to the pad and also to the transistor drain, and its cathode (302a) connected to power 303). These transistor and diode connections create a parasitic silicon controlled rectifier (SCR) with the SCR-anode (310a) formed by the diode anode, the first base region formed by the well, the second base region formed by the substrate, and the SCR-cathode (311a) formed by the transistor source. The SCR structure provides a significantly lower clamping voltage and an about two times higher failure current than a substrate-pumped MOS transistor.Type: GrantFiled: October 31, 2003Date of Patent: February 22, 2005Assignee: Texas Instruments IncorporatedInventors: Craig T. Salling, Charvaka Duvvury
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Patent number: 6835623Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.Type: GrantFiled: February 24, 2003Date of Patent: December 28, 2004Assignee: Texas Instruments IncorporatedInventors: Wei-Tsun Shiau, Craig T. Salling, Jerry Che-Jen Hu
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Publication number: 20040257853Abstract: Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.Type: ApplicationFiled: July 26, 2004Publication date: December 23, 2004Applicant: Micron Technology, Inc.Inventors: Craig T. Salling, Brian W. Huber