Patents by Inventor Craig Warner

Craig Warner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230343454
    Abstract: A method for the computer-assisted implementation of radiology recommendations includes any or all of: receiving a set of inputs; determining and/or identifying a set of findings; determining a set of follow-up recommendations; and triggering a set of outputs and/or actions based on the set of follow-up recommendations. A system for the computer-assisted implementation of radiology recommendations preferably includes and/or interfaces a set of computing subsystems and/or processing subsystems, but can additionally include and/or interface with a set of devices (e.g., user devices), models, and/or any other components.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Jeffrey Chang, Doktor Gurson, Scott Whitney, Joseph Zachary Allen, Shokoufeh Kazemlou, Maxwell Taylor, Craig Warner, Eric Purdy, Christopher Johnson
  • Publication number: 20230197276
    Abstract: A method for the computer-assisted implementation of radiology recommendations includes any or all of: receiving a set of inputs; determining and/or identifying a set of findings; determining a set of follow-up recommendations; and triggering a set of outputs and/or actions based on the set of follow-up recommendations. A system for the computer-assisted implementation of radiology recommendations preferably includes and/or interfaces a set of computing subsystems and/or processing subsystems, but can additionally include and/or interface with a set of devices (e.g., user devices), models, and/or any other components.
    Type: Application
    Filed: February 11, 2023
    Publication date: June 22, 2023
    Inventors: Jeffrey Chang, Doktor Gurson, Scott Whitney, Joseph Zachary Allen, Shokoufeh Kazemlou, Maxwell Taylor, Craig Warner, Eric Purdy
  • Patent number: 11615890
    Abstract: A method for the computer-assisted implementation of radiology recommendations includes any or all of: receiving a set of inputs; determining and/or identifying a set of findings; determining a set of follow-up recommendations; and triggering a set of outputs and/or actions based on the set of follow-up recommendations. A system for the computer-assisted implementation of radiology recommendations preferably includes and/or interfaces a set of computing subsystems and/or processing subsystems, but can additionally include and/or interface with a set of devices (e.g., user devices), models, and/or any other components.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: March 28, 2023
    Assignee: RAD AI, INC.
    Inventors: Jeffrey Chang, Doktor Gurson, Scott Whitney, Joseph Zachary Allen, Shokoufeh Kazemlou, Maxwell Taylor, Craig Warner, Eric Purdy
  • Patent number: 11532356
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: December 20, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Publication number: 20220293271
    Abstract: A method for the computer-assisted implementation of radiology recommendations includes any or all of: receiving a set of inputs; determining and/or identifying a set of findings; determining a set of follow-up recommendations; and triggering a set of outputs and/or actions based on the set of follow-up recommendations. A system for the computer-assisted implementation of radiology recommendations preferably includes and/or interfaces a set of computing subsystems and/or processing subsystems, but can additionally include and/or interface with a set of devices (e.g., user devices), models, and/or any other components.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 15, 2022
    Inventors: Jeffrey Chang, Doktor Gurson, Scott Whitney, Joseph Zachary Allen, Shokoufeh Kazemlou, Maxwell Taylor, Craig Warner, Eric Purdy
  • Publication number: 20220075597
    Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 10, 2022
    Inventors: Craig Warner, Eun Sub Lee, Sai Rahul Chalamalasetti, Martin Foltin
  • Publication number: 20210225440
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Patent number: 11024379
    Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 1, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit Sharma, John Paul Strachan, Suhas Kumar, Catherine Graves, Martin Foltin, Craig Warner
  • Publication number: 20210125667
    Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: AMIT SHARMA, JOHN PAUL STRACHAN, SUHAS KUMAR, CATHERINE GRAVES, MARTIN FOLTIN, CRAIG WARNER
  • Patent number: 10984860
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Publication number: 20210110243
    Abstract: Systems are methods are provided for implementing a deep learning accelerator system interface (DLASI). The DLASI connects an accelerator having a plurality of inference computation units to a memory of the host computer system during an inference operation. The DLASI allows interoperability between a main memory of a host computer, which uses 64 B cache lines, for example, and inference computation units, such as tiles, which are designed with smaller on-die memory using 16-bit words. The DLASI can include several components that function collectively to provide the interface between the server memory and a plurality of tiles. For example, the DLASI can include: a switch connected to the plurality of tiles; a host interface; a bridge connected to the switch and the host interface; and a deep learning accelerator fabric protocol. The fabric protocol can also implement a pipelining scheme which optimizes throughput of the multiple tiles of the accelerator.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 15, 2021
    Inventors: CRAIG WARNER, Chris Michael Brueggen, Eun Sub Lee
  • Patent number: 10847235
    Abstract: A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory location within a failed memory location. A wear-leveling rate on the memory module may be adjusted based on the remapping rate.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: November 24, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Ryan Akkerman, Craig Warner, Joseph Orth
  • Publication number: 20200312406
    Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Amit S. Sharma, John Paul Strachan, Catherine Graves, Suhas Kumar, Craig Warner, Martin Foltin
  • Patent number: 10776830
    Abstract: A method of providing services to computing devices includes establishing a connection over the Internet with a computing device; receiving data from the computing device during the connection; extracting a signal from the data received from the computing device; estimating a relative age of the computing device based on the extracted signal; selecting a service from a plurality of services based on the estimated relative age of the computing device; and providing the selected service to the computing device.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 15, 2020
    Assignee: Google LLC
    Inventors: Craig Warner, Timothy O'Connor, Alexander Ross, Gaurav Bhaya, Robert Stets
  • Patent number: 10474389
    Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: November 12, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Brian S. Birk, Joseph F. Orth, Harvey Ray, Craig Warner
  • Patent number: 10312943
    Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 4, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen, Brian S. Birk, Harvey Ray
  • Patent number: 10275307
    Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: April 30, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen
  • Patent number: 10152723
    Abstract: A method of providing services to computing devices includes establishing a connection over the Internet with a computing device; receiving data from the computing device during the connection; extracting a signal from the data received from the computing device; estimating a relative age of the computing device based on the extracted signal; selecting a service from a plurality of services based on the estimated relative age of the computing device; and providing the selected service to the computing device.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: December 11, 2018
    Assignee: Google LLC
    Inventors: Craig Warner, Timothy O'Connor, Alexander Ross
  • Publication number: 20180336034
    Abstract: In one example in accordance with the present disclosure, a compute engine block may comprise a data port connecting a processing core to a data cache, wherein the data port receives requests for accessing a memory and a data communication pathway to enable servicing of data requests of the memory. The processing core may be configured to identify a value in a predetermined address range of a first data request and adjust the bit size of a load instruction used by the processing core when a first value is identified.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 22, 2018
    Inventors: Craig Warner, Qiong Cai, Paolo Faraboschi, Gregg B Lesartre
  • Publication number: 20180276068
    Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 27, 2018
    Inventors: Gregg B. Lesartre, Craig Warner, Martin Foltin, Chris Michael Brueggen, Brian S. Birk, Harvey Ray