Abstract: A method of transmitting a data packet from a first virtualized server to a second virtualized server includes copying, by the first virtualized server, the data packet into a send queue associated with the first virtualized server, where the send queue is located at a fabric attached memory, where the fabric attached memory is accessible by the first virtualized server and the second virtualized server. The method further includes retrieving, by one or more processors associated with the fabric attached memory, the data packet from the send queue and forwarding, by the one or more processors, the data packet to a receive queue associated with the second virtualized server, where the receive queue is located at the fabric attached memory. The method further includes retrieving, by the second virtualized server, the data packet from the receive queue.

Abstract: Provided is a system configured for connecting to a host, including a memory protocol unit (MPU) configured for connecting one of at least two switch paths within the redundant array of independent devices (RAID) fabric to the host. The system also includes a RAID fabric including two or more leaf switches, each leaf switch including a routing processor coupled to the MPU along a respective one of the two switch paths, and a cluster of fault tolerant engines coupled to the routing processor, and a cluster of fabric fault tolerant CXL devices, each CXL device (i) coupled to a corresponding one of the fault tolerant engines and (ii) including a lock controller. The lock controller is configured to limit modifications to a parity group in the cluster of fabric fault tolerant CXL devices created via write requests and occurring during a single instance in time.

Abstract: Systems, methods, and computer-readable storage devices can include fabric networks for isolating and correcting failures in the fabric network and device failures. The fabric network connects to a group of devices and a host. The group of devices includes at least a target data device, other data devices, and a parity device. A redundant array of independent devices (RAID) engine, which is coupled to the one group of devices, performs an access operation. The fault tolerant engine is provided in a leaf switch of the fabric network. A routing processor determines a path for a request received from the host to the target data device. The routing processor is coupled to the fault tolerant engine, and the routing processor is provided in the leaf switch.

Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks.

Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks.

Abstract: A method for the computer-assisted implementation of radiology recommendations includes any or all of: receiving a set of inputs; determining and/or identifying a set of findings; determining a set of follow-up recommendations; and triggering a set of outputs and/or actions based on the set of follow-up recommendations. A system for the computer-assisted implementation of radiology recommendations preferably includes and/or interfaces a set of computing subsystems and/or processing subsystems, but can additionally include and/or interface with a set of devices (e.g., user devices), models, and/or any other components.

Abstract: A method for the computer-assisted implementation of radiology recommendations includes any or all of: receiving a set of inputs; determining and/or identifying a set of findings; determining a set of follow-up recommendations; and triggering a set of outputs and/or actions based on the set of follow-up recommendations. A system for the computer-assisted implementation of radiology recommendations preferably includes and/or interfaces a set of computing subsystems and/or processing subsystems, but can additionally include and/or interface with a set of devices (e.g., user devices), models, and/or any other components.

Abstract: A method for the computer-assisted implementation of radiology recommendations includes any or all of: receiving a set of inputs; determining and/or identifying a set of findings; determining a set of follow-up recommendations; and triggering a set of outputs and/or actions based on the set of follow-up recommendations. A system for the computer-assisted implementation of radiology recommendations preferably includes and/or interfaces a set of computing subsystems and/or processing subsystems, but can additionally include and/or interface with a set of devices (e.g., user devices), models, and/or any other components.

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Abstract: A method for the computer-assisted implementation of radiology recommendations includes any or all of: receiving a set of inputs; determining and/or identifying a set of findings; determining a set of follow-up recommendations; and triggering a set of outputs and/or actions based on the set of follow-up recommendations. A system for the computer-assisted implementation of radiology recommendations preferably includes and/or interfaces a set of computing subsystems and/or processing subsystems, but can additionally include and/or interface with a set of devices (e.g., user devices), models, and/or any other components.

Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks.

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.

Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state.

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Abstract: Systems are methods are provided for implementing a deep learning accelerator system interface (DLASI). The DLASI connects an accelerator having a plurality of inference computation units to a memory of the host computer system during an inference operation. The DLASI allows interoperability between a main memory of a host computer, which uses 64 B cache lines, for example, and inference computation units, such as tiles, which are designed with smaller on-die memory using 16-bit words. The DLASI can include several components that function collectively to provide the interface between the server memory and a plurality of tiles. For example, the DLASI can include: a switch connected to the plurality of tiles; a host interface; a bridge connected to the switch and the host interface; and a deep learning accelerator fabric protocol. The fabric protocol can also implement a pipelining scheme which optimizes throughput of the multiple tiles of the accelerator.

Abstract: A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory location within a failed memory location. A wear-leveling rate on the memory module may be adjusted based on the remapping rate.

Abstract: A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

Abstract: A method of providing services to computing devices includes establishing a connection over the Internet with a computing device; receiving data from the computing device during the connection; extracting a signal from the data received from the computing device; estimating a relative age of the computing device based on the extracted signal; selecting a service from a plurality of services based on the estimated relative age of the computing device; and providing the selected service to the computing device.

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.