Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

Abstract: A remapping rate of remapping operations on a memory module may be determined. Each remapping operation may comprise storing a pointer to an unfailed memory location within a failed memory location. A wear-leveling rate on the memory module may be adjusted based on the remapping rate.

Abstract: A method is provided. In an example, the method includes identifying a memory module that includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a plurality of memory regions, and each memory die of the plurality of memory dies services a respective portion of a data access. An error pattern is detected in a first memory region of the plurality of memory regions. The first memory region is associated with a first memory die of the plurality of memory dies. Based on the detected error pattern, the first memory region of the first memory die is marked as erased without marking a second memory region of the first memory die as erased.

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

Abstract: A method and system provide, using a microprocessor of computing device associated with a web publisher, content including a web page. The method includes accessing, by the web publisher, a list including at least one extension associated with a web browser rendering the content at a second computing device, and a key generated based on the content, the key being generated at a specific time after the providing. The method includes comparing a value associated with the key to an expected value to determine a difference between the key and the expected value.

Abstract: In various examples, device comprises a memory and a memory controller. The memory controller comprises a write tracking buffer. The memory controller to: receive a write request bound for the memory, store an entry associated with the write request in the write tracking buffer, and determine an access pattern of the memory. The access pattern indicates a high or a low write bandwidth of the memory. The memory controller to execute the write request bound for the memory based on the determined memory access pattern, complete execution of the write request, and responsive to completing execution of the write request, free the entry associated with the write request from the write tracking buffer.

Abstract: According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

Abstract: A method of providing services to computing devices includes establishing a connection over the Internet with a computing device; receiving data from the computing device during the connection; extracting a signal from the data received from the computing device; estimating a relative age of the computing device based on the extracted signal; selecting a service from a plurality of services based on the estimated relative age of the computing device; and providing the selected service to the computing device.

Abstract: A system includes a processor configured to execute a web browser in a first browser execution process initiated by an operating system of the system. The system includes a browser extension installed in the web browser, the browser extension including a markup language file and a file specifying at least one type of action related to a page element on which the browser extension seeks to act. The web browser may be configured to receive a set of rules from a web publisher associated with a first web page prior to rendering the first web page, determine based on the file, without loading the browser extension, that the browser extension is configured to implement a first action prohibited by the set of rules, and restrict the browser extension from implementing the first action on the first web page.

Abstract: A controller has a cache to store data associated with an address that is subject to conflict resolution. A conflict resolution queue stores information relating to plural transactions, and logic reprioritizes the plural transactions in the conflict resolution queue to change a priority of a first type of transaction with respect to a priority of second type of transaction.

Abstract: A method of shielding a memory device (110) from high write rates comprising receiving instructions to write data at a memory container (105), the memory controller (105) composing a cache (120) comprising a number of cache lines defining stored data, with the memory controller (105), updating a cache line in response to a write hit in the cache (120), and with the memory controller (105), executing the instruction to write data in response to a cache miss to a cache line within the cache (120) in which the memory controller (105) prioritizes for writing to the cache (120) over writing to the memory device (110).

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors. In a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.

Abstract: According to an example, a multi-mode agent may include a processor interconnect (PI) interface to receive data from a processor and to selectively route the data to a node controller logic block, a central switch, or an optical interface based on one of a plurality of modes of operation of the multi-mode agent. The modes of operation may include a glueless mode where the PI interface is to route the data directly to the optical interface and bypass the node controller logic block and the central switch, a switched glueless mode where the PI interface is to route the data directly to the central switch for routing to the optical interface, and bypass the node controller logic block, and a glued mode where the PI interface is to route the data directly to the node controller logic block for routing to the central switch and further to the optical interface.

Abstract: A method and system provide, using a microprocessor of computing device associated with a web publisher, content including a web page. The method includes accessing, by the web publisher, a list including at least one extension associated with a web browser rendering the content at a second computing device, and a key generated based on the content, the key being generated at a specific time after the providing. The method includes comparing a value associated with the key to an expected value to determine a difference between the key and the expected value.

Abstract: In one aspect, the subject disclosure can be embodied in a method for building desktop applications using a web browser platform is provided. A content type and a location of a web application is determined based on input from a user via an input field. Application data for the web application is retrieved based on the determined content type and location of the web application. Parameters for a browser platform application to be generated for the web application are identified, and the browser platform application is generated based on the retrieved application data and the identified parameters.

Abstract: A method of shielding a memory device (110) from high write rates comprising receiving instructions to write data at a memory container (105), the memory controller (105) composing a cache (120) comprising a number of cache lines defining stored data, with the memory controller (105), updating a cache line in response to a write hit in the cache (120), and with the memory controller (105), executing the instruction to write data in response to a cache miss to a cache line within the cache (120) in which the memory controller (105) prioritizes for writing to the cache (120) over writing to the memory device (110).

Abstract: A controller has a cache to store data associated with an address that is subject to conflict resolution. A conflict resolution queue stores information relating to plural transactions, and logic reprioritizes the plural transactions in the conflict resolution queue to change a priority of a first type of transaction with respect to a priority of second type of transaction.

Abstract: A computing device includes a home node controller to couple a home processor socket to the computing device. The home processor socket includes a home core hidden from the computing device and the home core fetches data to a home cache of the home processor socket. The computing device includes a source processor socket including a source core to request for data and the home node controller forwards requested data from the home cache to the source core if the requested data is included on the home cache.

Abstract: A computer apparatus and related method to access storage is provided. In one aspect, a controller maps an address range of a data block of storage into an accessible memory address range of at least one of a plurality of processors, in a further aspect, the controller ensures that copies of the data block cached in a plurality of memories by a plurality of processors are consistent.