Patents by Inventor Cristiano Gianluca STELLA

Cristiano Gianluca STELLA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240234263
    Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.
    Type: Application
    Filed: October 24, 2023
    Publication date: July 11, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Fabio RUSSO
  • Publication number: 20240206133
    Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 20, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Francesco SALAMONE
  • Publication number: 20240203837
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 20, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Fabio Vito COPPONE, Francesco SALAMONE
  • Publication number: 20240136260
    Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Fabio RUSSO
  • Patent number: 11894290
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: February 6, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Fabio Vito Coppone, Francesco Salamone
  • Patent number: 11864361
    Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 2, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Francesco Salamone
  • Patent number: 11830794
    Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: November 28, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cristiano Gianluca Stella, Fabio Russo
  • Publication number: 20230317685
    Abstract: Electronic device comprising at least a first and a second branch, each branch including a first and a second transistor arranged in series to each other and formed in respective dice of semiconductor material. The dice are sandwiched between a first substrate element and a second substrate element. The first and the second substrate elements are formed each by a multilayer including a first conductive layer, a second conductive layer and an insulating layer extending between the first and the second conductive layers. The first conductive layers of the first and the second substrate elements face towards the outside of the electronic device and define a first and a second main face of the electronic device. The second conductive layer of the first and the second substrate elements is shaped so as to form contact regions facing and in selective electrical contact with the plurality of dice.
    Type: Application
    Filed: March 23, 2023
    Publication date: October 5, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Agatino MINOTTI, Francesco SALAMONE
  • Publication number: 20230282564
    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
    Type: Application
    Filed: April 24, 2023
    Publication date: September 7, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Agatino MINOTTI
  • Patent number: 11658108
    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 23, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Agatino Minotti
  • Publication number: 20230143679
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 11, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Fabio Vito COPPONE, Francesco SALAMONE
  • Patent number: 11562950
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: January 24, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cristiano Gianluca Stella, Fabio Vito Coppone, Francesco Salamone
  • Publication number: 20220199563
    Abstract: The packaged power electronic device has a bearing structure including a base section and a transverse section extending transversely to the base section. A die is bonded to the base section of the bearing structure and has a first terminal on a first main face and a second and a third terminal on a second main face. A package of insulating material embeds the semiconductor die, the second terminal, the third terminal and at least partially the carrying base. A first, a second and a third outer connection region are electrically coupled to the first, the second and the third terminals of the die, respectively, are laterally surrounded by the package and face the second main surface of the package. The transverse section of the bearing structure extends from the base section towards the second main surface of the package and has a higher height with respect to the die.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 23, 2022
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca STELLA, Roberto RIZZA
  • Patent number: 11239132
    Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: February 1, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Salamone, Cristiano Gianluca Stella
  • Publication number: 20220013439
    Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 13, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cristiano Gianluca STELLA, Fabio RUSSO
  • Publication number: 20210327792
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Application
    Filed: April 9, 2021
    Publication date: October 21, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cristiano Gianluca STELLA, Fabio Vito COPPONE, Francesco SALAMONE
  • Publication number: 20210159161
    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
    Type: Application
    Filed: January 6, 2021
    Publication date: May 27, 2021
    Inventors: Cristiano Gianluca STELLA, Agatino MINOTTI
  • Publication number: 20210037674
    Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
    Type: Application
    Filed: July 21, 2020
    Publication date: February 4, 2021
    Inventors: Cristiano Gianluca STELLA, Francesco SALAMONE
  • Patent number: 10910302
    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Agatino Minotti
  • Publication number: 20200303278
    Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Francesco SALAMONE, Cristiano Gianluca STELLA