Patents by Inventor Cuiqin XU

Cuiqin XU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180286967
    Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Jing WAN, Jer-Hueih(James) CHEN, Cuiqin XU, Padmaja NAGAIAH
  • Patent number: 10020383
    Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jing Wan, Jer-Hueih(James) Chen, Cuiqin Xu, Padmaja Nagaiah
  • Patent number: 9741853
    Abstract: Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: August 22, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mantavya Sinha, Prasanna Kannan, Cuiqin Xu, Tao Wang, Suresh Kumar Regonda
  • Publication number: 20170125587
    Abstract: Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate having a channel region underlying, at least partially, the gate structure, the fabricating involving: performing a nitrogen ion implantation process by implanting nitrogen ions into the substrate to thereby form a stress region in the substrate, the stress region separated by the channel region, wherein the stress region has a stress region depth; forming a capping material layer above the NMOS transistor device; and, with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the stress region. In another embodiment, an amorphization ion implantation is performed prior to, after or along with the nitrogen ion implantation.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Mantavya SINHA, Prasanna KANNAN, Cuiqin XU, Tao WANG, Suresh Kumar REGONDA
  • Publication number: 20160343607
    Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 24, 2016
    Inventors: Jing WAN, Jer-Hueih(James) CHEN, Cuiqin XU, Padmaja NAGAIAH
  • Patent number: 9231079
    Abstract: One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Johannes M. van Meer, Cuiqin Xu, Isabelle Ferain
  • Publication number: 20150364570
    Abstract: One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.
    Type: Application
    Filed: June 13, 2014
    Publication date: December 17, 2015
    Inventors: Johannes M. van Meer, Cuiqin Xu, Isabelle Ferain
  • Publication number: 20150303295
    Abstract: Approaches for forming a set of contact openings in a semiconductor device (e.g., a FinFET device) are provided. Specifically, the semiconductor device includes a set of fins formed in a substrate, a gate structure (e.g., replacement metal gate (RMG)) formed over the substrate, and a set of contact openings adjacent the gate structure, each of the set of contact openings having a top section and a bottom section, wherein a width of the bottom section, along a length of the gate structure, is greater than a width of the top section. The semiconductor device further includes a set of metal contacts formed within the set of contact openings.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 22, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing Wan, Xiang Hu, Jinping Liu, Gabriel Padron Wells, Andy Chih-Hung Wei, Guillaume Bouche, Cuiqin Xu
  • Patent number: 9129987
    Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 8, 2015
    Assignee: GLOBAL FOUNDRIES, Inc.
    Inventors: Jing Wan, Jin Ping Liu, Guillaume Bouche, Andy Wei, Lakshmanan H. Vanamurthy, Cuiqin Xu, Sridhar Kuchibhatla, Rama Kambhampati, Xiuyu Cai
  • Publication number: 20150214330
    Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing WAN, Jin Ping LIU, Guillaume BOUCHE, Andy WEI, Lakshmanan H. VANAMURTHY, Cuiqin XU, Sridhar KUCHIBHATLA, Rama KAMBHAMPATI, Xiuyu CAI
  • Publication number: 20150214345
    Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) are provided. Specifically, the device comprises a gate structure formed over a substrate, a source and drain (S/D) embedded within the substrate adjacent the gate structure, and a liner layer (e.g., silicon-carbon) between the S/D and the substrate. In one approach, the liner layer is formed atop the S/D as well. As such, the liner layer formed in the junction prevents dopant diffusion from the source/drain.
    Type: Application
    Filed: January 27, 2014
    Publication date: July 30, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing Wan, Jinping Liu, Churamani Gaire, Mariappan Hariharaputhiran, Andy Chih-Hung Wei, Bharat V. Krishnan, Cuiqin Xu, Michael Ganz