STRESS MEMORIZATION TECHNIQUES FOR TRANSISTOR DEVICES
One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.
1. Field of the Disclosure
The present disclosure generally relates to the formation of semiconductor devices and, more specifically, to various stress memorization techniques that may be employed when manufacturing transistor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on current generation transistor devices may be approximately 20-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure, etc. Another technique that device designers have employed to improve device performance is to induce a desired stress in the channel region of a device, i.e., induce a tensile stress in the channel region of an NMOS device (to improve the mobility of charge-carrying electrons) and induce a compressive stress in the channel region of a PMOS device (to improve the mobility of charge-carrying holes). Various stress-memorization techniques are known to those skilled in the art.
One typical prior art process flow that is performed to form NMOS transistors with the desired tensile stress in a CMOS application is as follows. After the gate structures are formed, N-type extension implants are formed for the N-type devices with the P-type devices masked, a first spacer is formed on both the N- and P-type devices, extension and halo implants are performed on the P-type devices with the N-type devices masked, a second spacer is formed of the P-type devices, a cavity is etched in the source/drain regions of the P-type devices and an epi semiconductor material is formed in the cavities on the P-type devices. Thereafter, a second spacer is formed on the N-type devices, an amorphization implant process (Germanium—55 keV, 3e14 ion/cm2 dose) is performed using a material such as germanium to amorphize the source/drain region. Next, a so-called SMT (Stress Memorization Techniques) processing module is performed on the N-type device. The SMT module involves forming a layer of silicon dioxide (e.g., about 4 nm thick) on the substrate, forming a capping material layer, e.g., a thick layer of silicon nitride (e.g., about 40 nm thick) with the desired intrinsic stress, heating the device for about 10 minutes at 750° C. in a nitrogen environment. Thereafter, the layer of silicon nitride and the layer of silicon dioxide are removed by performing one or more etching processes. Then, raised source/drain regions are formed by depositing epi semiconductor material in the source/drain areas of the device. Thereafter, deep source/drain implant regions are formed by performing an ion implantation process. A heating process is later performed to repair damage to the lattice structure of the substrate due to the amorphization implant process and the other ion implantation processes that were performed on the substrate up to this point in the process flow.
The present disclosure is directed to various stress memorization techniques that may reduce or eliminate one or more of the problems identified above.
SUMMARYThe following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the disclosure. This summary is not an exhaustive overview. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various stress memorization techniques that may be employed when manufacturing transistor devices. One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation process with a dopant material to thereby form a doped extension implant region in the source/drain regions, performing a Group VII material ion implantation process on the source/drain regions with a Group VII material, after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions and with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.
Another illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation process with a dopant material to thereby form a doped extension implant region in the source/drain regions, performing an amorphization ion implantation process on the source/drain regions, performing a Group VII material ion implantation process on the source/drain regions with a Group VII material, after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.
Yet another illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation process with an N-type dopant material to thereby form a doped extension implant region in the source/drain regions, performing an amorphization ion implantation process on the source/drain regions, performing a fluorine ion implantation process on the source/drain regions, after performing the fluorine ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims.
NOTATION AND NOMENCLATURECertain terms are used throughout the disclosure to refer to particular components. However, different entities may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. The terms “including” and “comprising” are used herein in open-ended fashion, and thus mean “including, but not limited to.”
DETAILED DESCRIPTIONThe present subject matter will now be described with reference to the attached figures. Various structures, systems, and devices are schematically depicted in the drawings for purposes of explanation only. The attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those in the industry. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those in the industry, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various stress memorization techniques that may be employed when manufacturing transistor devices. As will be readily apparent, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc., and the methods disclosed herein may be employed to form N-type or P-type semiconductor devices. Additionally, various doped regions, e.g., source/drain regions, halo implant regions, well regions and the like, are not depicted in the attached drawings. Of course, the inventions disclosed herein should not be considered to be limited to the illustrative examples depicted and described herein. The various components and structures of the device 100 disclosed herein may be formed using a variety of different materials and by performing a variety of known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, etc. The thicknesses of these various layers of material may also vary depending upon the particular application. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
The inventors have discovered that, by performing a implantation process using a Group VII material (from the periodic table), such as fluorine, such stacking faults may be desirably formed for devices having a very small LOD (Length of Diffusion the dimension between the edge of the gate structure at issue and the edge of the active region), even for devices that are located adjacent the free surface of the active region, i.e., the interface between the active region and the isolation material.
As indicated in
Some prior art methods have been attempted to improve the formation of the desired stress in N-type transistors. One prior art technique involves formation of a hydrogen-rich silicon nitride layer as a stress memorization layer in an effort to form the desired stacking faults 114 in N-type devices. However, such attempts have typically resulted in only, at best, the partial formation of the desired stacking faults 114 in the source/drain region of the device and only for tucked devices. Untucked devices did not show any appreciable stacking faults using this prior art method.
At the point of fabrication depicted in
With continuing reference to
As shown in
It should be noted that, as will be appreciated by those skilled in the art, the present invention is not limited to devices 200 where raised source/drain regions are formed. In applications where the device 200 includes traditional non-raised source/drain regions, the above described Group VII implantation process 232 may be performed after the above-described deep source/drain implant process 250 was performed. In such an example, the method would then involve formation of the liner layer 234 and the capping material layer 236 and thereafter performing the above-described anneal process 240 to produce the desired stacking faults 242.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Note that the use of terms, such as “first,” “second,” “third” or “fourth” to describe various processes or structures in this specification and in the attached claims is only used as a shorthand reference to such steps/structures and does not necessarily imply that such steps/structures are performed/formed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A method of forming a transistor device comprising a gate structure and a plurality of source/drain regions, the method comprising:
- performing a source/drain extension ion implantation process with a dopant material to thereby form a doped extension implant region in said source/drain regions;
- performing a Group VII material ion implantation process on said source/drain regions with a Group VII material;
- after performing said Group VII material ion implantation process, forming a capping material layer above said source/drain regions;
- with said capping material layer in position, performing an anneal process so as to form stacking faults in said source/drain regions;
- removing said capping material layer;
- forming epi semiconductor material for said source/drain regions after removing said capping material layer;
- performing a deep source/drain ion implantation process with a dopant material after forming said epi semiconductor material; and
- performing a second anneal process to activate implanted dopant materials from said deep source/drain ion implantation process.
2. The method of claim 1, wherein said transistor is an NMOS transistor.
3. (canceled)
4. The method of claim 1, wherein said gate structure comprises a high-k gate insulation layer and a gate electrode comprised of at least one layer of metal.
5. The method of claim 1, wherein said gate structure comprises a silicon dioxide gate insulation layer and a gate electrode comprised of a layer of polysilicon.
6. The method of claim 1, wherein said Group VII material is fluorine.
7. The method of claim 1, further comprising performing an amorphization ion implantation process on said source/drain regions prior to performing said Group VII material ion implantation process.
8. The method of claim 1, further comprising performing an amorphization ion implantation process on said source/drain regions after performing said Group VII material ion implantation process.
9. The method of claim 1, wherein said Group VII material ion implantation process amorphizes a portion of said source/drain regions.
10. The method of claim 7, wherein said amorphization ion implantation process is performed using germanium or silicon.
11. The method of claim 1, wherein said anneal process is performed in an inert process ambient at a temperature of at least about 600° C.
12. The method of claim 1, wherein said Group VII material ion implantation process is performed using an implant energy that falls within the range of 1-30 keV and a dose of said Group VII material that falls within the range of 1e14-1e16 ions/cm2.
13. The method of claim 7, wherein said amorphization implantation process is performed using an implant energy that falls within the range of about 10-100 keV and an implant dose of about 1e14-1e16 ions/cm2.
14. A method of forming a transistor device comprising a gate structure and a plurality of source/drain regions, the method comprising:
- performing a source/drain extension ion implantation process with a dopant material to thereby form a doped extension implant region in said source/drain regions;
- performing an amorphization ion implantation process on said source/drain regions;
- performing a Group VII material ion implantation process on said source/drain regions with a Group VII material;
- after performing said Group VII material ion implantation process, forming a capping material layer above said source/drain regions;
- with said capping material layer in position, performing an anneal process so as to form stacking faults in said source/drain regions;
- removing said capping material layer;
- forming epi semiconductor material for said source/drain regions after removing said capping material layer;
- performing a deep source/drain ion implantation process with a dopant material after forming said epi semiconductor material; and
- performing a second anneal process to activate implanted dopant materials from said deep source/drain ion implantation process.
15. (canceled)
16. The method of claim 14, wherein said Group VII material is fluorine.
17. The method of claim 14, wherein said amorphization ion implantation process is performed prior to performing said Group VII material ion implantation process.
18. The method of claim 14, wherein said amorphization ion implantation process is performed after performing said Group VII material ion implantation process.
19. The method of claim 14, wherein said amorphization ion implantation process is performed using germanium or silicon.
20. The method of claim 14, wherein said anneal process is performed in an inert process ambient at a temperature of at least about 600° C.
21. A method of forming an NMOS transistor device comprising a gate structure and a plurality of source/drain regions, the method comprising:
- performing a source/drain extension ion implantation process with an N-type dopant material to thereby form a doped extension implant region in said source/drain regions;
- performing an amorphization ion implantation process on said source/drain regions;
- performing a fluorine ion implantation process on said source/drain regions;
- after performing said fluorine ion implantation process, forming a capping material layer above said source/drain regions;
- with said capping material layer in position, performing an anneal process so as to form stacking faults in said source/drain regions;
- removing said capping material layer;
- forming epi semiconductor material for said source/drain regions after removing said capping material layer;
- performing a deep source/drain ion implantation process with a dopant material after forming said epi semiconductor material; and
- performing a second anneal process to activate implanted dopant materials from said deep source/drain ion implantation process.
22. The method of claim 21, wherein said capping material layer is a layer of silicon nitride.
23. (canceled)
24. The method of claim 21, wherein said amorphization ion implantation process is performed prior to said fluorine ion implantation process.
25. The method of claim 21, wherein said amorphization ion implantation process is performed after said fluorine ion implantation process.
26. The method of claim 21, wherein said amorphization ion implantation process is performed using germanium, silicon or fluorine.
27. The method of claim 21, wherein said anneal process is performed in an inert process ambient at a temperature of at least about 600° C.
28. The method of claim 21, wherein said fluorine ion implantation process is performed using an implant energy that falls within the range of 1-30 keV and a dose of fluorine that falls within the range of 1e14-1e16 ions/cm2.
Type: Application
Filed: Jun 13, 2014
Publication Date: Dec 17, 2015
Inventors: Johannes M. van Meer (Delmar, NY), Cuiqin Xu (Malta, NY), Isabelle Ferain (Ballston Spa, NY)
Application Number: 14/304,017