Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

Abstract: Methods of fabricating a flexible dummy fill to increase MTJ density are provided. Embodiments include forming a first oxide layer; forming lower interconnect layers in the first oxide layer; forming a nitride layer over the first oxide layer and the lower interconnect layers; forming a second oxide layer over the nitride layer; forming bottom electrodes through the second oxide layer and the nitride layer contacting a portion of an upper surface of the lower interconnect layers; forming MTJ structures over the bottom electrodes; forming top electrodes over the MTJ structures; and forming upper interconnect layers over one or more of the top electrodes.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a memory cell with a memory cell upper surface. A capping layer is formed overlying the memory cell, and a portion of the capping layer is removed to expose the memory cell upper surface. A memory cell etch stop is formed overlying the memory cell upper surface after the portion of the capping layer is removed to expose the memory cell upper surface. The memory cell etch stop is removed from overlying the memory cell upper surface, and an interconnect is formed in electrical communication with the memory cell.

Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.

Abstract: Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (MTJ) structures are provided. An exemplary method for fabricating an integrated circuit includes forming an MTJ structure including a top electrode layer. The MTJ structure has a first sidewall and a second sidewall separated from the first sidewall by a first width. The method includes forming a conductive etch stop on the top electrode layer. The conductive etch stop has a second width greater than the first width. The method also includes depositing dielectric material over the conductive etch stop and the MTJ structure. The method further includes etching the dielectric material to form a trench exposing the conductive etch stop. Also, the method includes forming a conductive via in the trench over and in electrical communication with the conductive etch stop.

Abstract: High density resistive memory structures, integrate circuits with high density resistive memory structures, and methods for fabricating high density resistive memory structures are provided. In an embodiment, a high density resistive memory structure includes a semiconductor substrate and a plurality of first electrodes in a first plane in and/or over the semiconductor substrate. Further, the high density resistive memory structure includes a plurality of second electrodes in a second plane in and/or over the semiconductor substrate. The second plane is parallel to the first plane, and each second electrode in the plurality of second electrodes crosses over or under each first electrode in the plurality of first electrodes at a series of cross points. Each second electrode in the plurality of second electrodes is non-linear and the series of cross points formed by each respective second electrode is non-linear.

Abstract: Methods of fabricating a dome-shaped MTJ TE and the resulting devices are provided. Embodiments include forming a MRAM stack having a laterally separated MTJ structures and the MRAM and a logic stack each having a SiN layer; forming first trenches through the MRAM stack to a portion of the SiN layer above an MTJ structure; forming second trenches through the SiN layer fully landing on an upper portion of the MTJ structures and removing the SiN layer of the logic stack; forming a TaN layer over the MRAM and logic stack; removing portions of the TaN layer on opposite sides of the MTJ structures and therebetween; forming an oxide layer over the MRAM and logic stacks; and forming vias through the oxide layer of the MRAM stack down the TaN layer above MTJ structures and a via through the logic stack.

Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions and providing a plurality of interlevel dielectric (ILD) levels having tight pitch over the first and second regions of the substrate. An ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds to Mx, an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes via level Vx and metal level Mx+1 and the next overlying ILD level corresponds to a third ILD level includes via level Vx+1 and metal level Mx+2. The method includes forming a two-terminal device element is formed in between metal level Mx and via level Vx+1 in the first region.

Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions and providing a plurality of interlevel dielectric (ILD) levels having tight pitch over the first and second regions of the substrate. An ILD level of which a two-terminal element disposed thereon corresponds to a first ILD level and its metal level corresponds to Mx, an immediate ILD level overlying the metal level Mx corresponds to a second ILD level includes via level Vx and metal level Mx+1 and the next overlying ILD level corresponds to a third ILD level includes via level Vx+1 and metal level Mx+2. The method includes forming a two-terminal device element is formed in between metal level Mx and via level Vx+1 in the first region.