Patents by Inventor D. Michael Bell
D. Michael Bell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7535918Abstract: In one embodiment, a data movement module (DMM) may receive a command to copy data from a source buffer to a destination buffer. One or more cache lines corresponding to addresses of the source buffer and the destination buffer may be invalidated. Also, an entry may be added to a queue to indicate that the command to copy is completion pending.Type: GrantFiled: June 30, 2005Date of Patent: May 19, 2009Assignee: Intel CorporationInventors: Anil Vasudevan, D. Michael Bell, Sujoy Sen, Parthasarathy Sarangam
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Patent number: 7480747Abstract: Some embodiments include apparatus and method having a register circuit to receive a first portion of a packet from an input/output device, cache memory circuit to receive a second portion of the package, and a processing unit to process at least one of the first and second portions of the packet based on instructions in the processing unit. The processing unit and the register circuit reside on a processor. The first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor. The second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.Type: GrantFiled: June 8, 2005Date of Patent: January 20, 2009Assignee: Intel CorporationInventors: D. Michael Bell, Anil Vasudevan
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Patent number: 7107371Abstract: A system and method for sending device specific data in a bus transaction. A device configurable field is preallocated in a packet sent by the sending device to a receiving device. The sending device can configure the data to be stored in the device configurable field. Upon receipt of the packet, the receiving device generates a response packet in which the contents of the device configurable field is simply copied into a corresponding field in the response packet.Type: GrantFiled: September 22, 1997Date of Patent: September 12, 2006Assignee: Intel CorporationInventor: D. Michael Bell
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Patent number: 7016989Abstract: A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as to the skew is distributed over multiple clock periods.Type: GrantFiled: December 23, 1999Date of Patent: March 21, 2006Assignee: Intel CorporationInventor: D. Michael Bell
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Publication number: 20030041212Abstract: A caching input/output hub includes a host interface to connect with a host. At least one input/output interface is provided to connect with an input/output device. A write cache manages memory writes initiated by the input/output device. At least one read cache, separate from the write cache, provides a low-latency copy of data that is most likely to be used. The at least one read cache is in communication with the write cache. A cache directory is also provided to track cache lines in the write cache and the at least one read cache. The cache directory is in communication with the write cache and the at least one read cache.Type: ApplicationFiled: August 27, 2001Publication date: February 27, 2003Inventors: Kenneth C. Creta, D. Michael Bell, Robert George, Bradford Congdon, Robert Blankenship, Duane January
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Patent number: 6330630Abstract: A bus bridge receives an inbound read request from a master. In response to the read request, the bridge transmits multiple (e.g., two) read request packets to fetch data. The fetched data is stored in the bridge when it returns. When the master returns for its data, the data from each packet is transferred to the master if the data is valid. By issuing two smaller read request packets in response to an inbound read request, inbound read latency is reduced. In addition, if only a single master is being serviced, the system speculatively prefetches data for the master when the master returns to receive its data. Also, if the master is disconnected before completing the data transfer, the data can be subsequently restreamed from the bridge if the data is still valid when the master reconnects.Type: GrantFiled: March 12, 1999Date of Patent: December 11, 2001Assignee: Intel CorporationInventor: D. Michael Bell
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Patent number: 6317799Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.Type: GrantFiled: April 28, 2000Date of Patent: November 13, 2001Assignee: Intel CorporationInventors: William T. Futral, D. Michael Bell
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Patent number: 6266778Abstract: A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.Type: GrantFiled: August 25, 1999Date of Patent: July 24, 2001Assignee: Intel CorporationInventor: D. Michael Bell
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Patent number: 6148356Abstract: A computer system includes a host processor coupled to a host bus. A bridge controller is coupled to the host bus and to a plurality of first buses. The computer system also includes one or more bus bridges, each coupled to the bridge controller via one or more of said first buses. Each bus bridge is connected to one or more second buses. Either the first buses or the second buses are each configurable in either an independent mode in which the bus operates independently, or a combined mode in which two or more of said first buses or said second buses are combined to create a single bus.Type: GrantFiled: January 26, 1998Date of Patent: November 14, 2000Assignee: Intel CorporationInventors: David W. Archer, D. Michael Bell, Doug Moran, Steve Pawlowski
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Patent number: 6134622Abstract: A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently and a combined mode in which the first and second external buses are combined to create a single bus. The bus expander bridge includes a first set of data queues for routing data between the first external bus and the third bus, and a second set of data queues for routing data between the second external bus and the third bus. The bus expander bridge also includes a controller coupled to the first and second sets of data queues and operating the first and second sets of data queues in parallel for the independent mode. The controller routes even addressed data through the first set of data queues and routes odd addressed data through the second set of data queues for the combined mode.Type: GrantFiled: January 26, 1998Date of Patent: October 17, 2000Assignee: Intel CorporationInventors: Suvansh Kapur, Kevin Koschoreck, Srinand Venkatesan, D. Michael Bell
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Patent number: 6108736Abstract: A system and method for controlling the flow of information between devices. A count is maintained representative of requests issued by a first device. The count is incremented for each packet issued by a first device and decremented for each packet received at the first device. A maximum buffer count, which corresponds to the capacity of the buffer is used to perform flow control by determining when the maximum buffer count is to be exceeded by the issuance of a packet by the first device. If the count is to be exceed, issuance of packets by the first device is prevented until the maximum buffer count will not be exceeded by issuance of the packet.Type: GrantFiled: September 22, 1997Date of Patent: August 22, 2000Assignee: Intel CorporationInventor: D. Michael Bell
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Patent number: 6088370Abstract: A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as the skew is distributed over multiple clock periods.Type: GrantFiled: September 22, 1997Date of Patent: July 11, 2000Assignee: Intel CorporationInventor: D. Michael Bell
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Patent number: 6081851Abstract: The invention, in one embodiment, is a method for accessing memory. The method includes programming a remote DMA engine from a destination; accessing data in the memory with the DMA engine, the DMA engine operating as programmed by the destination; and transferring the accessed data to the destination.Type: GrantFiled: December 15, 1997Date of Patent: June 27, 2000Assignee: Intel CorporationInventors: William T. Futral, D. Michael Bell
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Patent number: 6070207Abstract: A computer system includes a host processor coupled to a host bus. The computer system also includes a memory system coupled to the host bus, and an I/O bridge controller coupled to the host bus and including a plurality of ports. An I/O bus bridge is provided that is hot plug connectable to at least one of the bridge controller ports via one or more first buses. There are one or more second buses coupled to the I/O bus bridge.Type: GrantFiled: August 20, 1998Date of Patent: May 30, 2000Assignee: Intel CorporationInventor: D. Michael Bell
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Patent number: 6047120Abstract: The dual mode bus bridge accommodates either two 64-bit personal computer interface (PCI) buses or four 32-bit PCI buses. In either case, only a single load is applied to the host bus. The dual mode bridge includes a bridge controller unit connected to a pair of expansion bridge units by respective internal buses. Each expansion bridge unit includes two sets of 64-bit wide queues and buffers. For 32-bit PCI operation, the two sets of queues and buffers are operated in parallel. For 64-bit PCI operation, the two sets of queues and buffers are linked together so as to appear in series to provide a single queue structure having twice the depth of the separate queue structures for a 32-bit mode operation. As such, undue duplication of queue and buffer resources is avoided. Method and apparatus embodiments of the invention are described.Type: GrantFiled: September 9, 1998Date of Patent: April 4, 2000Assignee: Intel CorporationInventor: D. Michael Bell
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Patent number: 6021451Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.Type: GrantFiled: September 17, 1998Date of Patent: February 1, 2000Assignee: Intel CorporationInventors: D. Michael Bell, Mark A. Gonzales, Susan S. Meredith
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Patent number: 5905876Abstract: A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.Type: GrantFiled: December 16, 1996Date of Patent: May 18, 1999Assignee: Intel CorporationInventors: Stephen S. Pawlowski, Peter D. MacWilliams, D. Michael Bell
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Patent number: 5835739Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.Type: GrantFiled: July 10, 1997Date of Patent: November 10, 1998Assignee: Intel CorporationInventors: D. Michael Bell, Mark A. Gonzales, Susan S. Meredith
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Patent number: 5828865Abstract: The dual mode bus bridge accommodates either two 64-bit personal computer interface (PCI) buses or four 32-bit PCI buses. In either case, only a single load is applied to the host bus. The dual mode bridge includes a bridge controller unit connected to a pair of expansion bridge units by respective internal buses. Each expansion bridge unit includes two sets of 64-bit wide queues and buffers. For 32-bit PCI operation, the two sets of queues and buffers are operated in parallel. For 64-bit PCI operation, the two sets of queues and buffers are linked together so as to appear in series to provide a single queue structure having twice the depth of the separate queue structures for a 32-bit mode operation. As such, undue duplication of queue and buffer resources is avoided. Method and apparatus embodiments of the invention are described.Type: GrantFiled: December 27, 1995Date of Patent: October 27, 1998Assignee: Intel CorporationInventor: D. Michael Bell
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Patent number: 5594882Abstract: A scheme for providing split transaction capability on a PCI standard bus without modification to the existing PCI standard. Additional address bits are provided to a standard PCI address signal. The additional bits carry information regarding the requestor of a read transaction. By providing the requestor's identification to an addressed target, data is provided by the target device as a posted write. By using this enhanced mode, read requests need not be continually retried. If a target device is unable to respond to the enhanced address signal, the transaction is resent as a standard PCI address signal with the enhanced bits turned off.Type: GrantFiled: January 4, 1995Date of Patent: January 14, 1997Assignee: Intel CorporationInventor: D. Michael Bell