Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Decoding circuitry within the bridge issues a deferred response if the request can be deferred. This deferred response is returned to the originating agent on the first bus, thereby informing the originating agent that the request will be serviced at a later time. Bus control circuitry coupled to the outbound request queue removes requests from the outbound request queue and executes them on the second bus. The bus control circuitry receives a response from the destination agent on the second bus in response to the execution of the outbound request. This response is returned to the originating agent either immediately or after passing through an inbound request queue.

Abstract: A circuit within a bus bridge operating in a first clock domain and a second clock domain, wherein the circuit allows data, address or any other information to be reliably transferred between the first and second clock domains regardless whether or not an internal bus clock of the second clock domain is operating in a synchronous or asynchronous fashion, while the circuit still minimizes clock skew between the internal bus clocks of both clock domains as well as any corresponding external bus clocks.

Abstract: A computer system bootstrap loads a processor and associated memory from an external memory device instead of being bootstrap loaded from on-board read only memory. The computer system is comprised of a system bus, a processing component, a first system memory device, a memory card interface controller, and an external memory device connected to the memory card interface controller. The system also includes a second system memory device, a keyboard memory device, a keyboard controller and a reset switch for causing a reset and initialization of the processing component. Upon reset, the logic in the memory card interface controller remaps the address space associated with the first system memory device to the external memory device and remaps the address space associated with the second system memory device to the keyboard memory device.