Patents by Inventor D. V. Nirmal Ramaswamy
D. V. Nirmal Ramaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446751Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.Type: GrantFiled: January 17, 2018Date of Patent: October 15, 2019Assignee: Micron Technology, Inc.Inventors: Christopher W. Petz, Yongjun Jeff Hu, Scott E. Sills, D. V. Nirmal Ramaswamy
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Publication number: 20190311767Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: ApplicationFiled: June 11, 2019Publication date: October 10, 2019Applicant: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Patent number: 10418554Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.Type: GrantFiled: October 26, 2018Date of Patent: September 17, 2019Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, D. V. Nirmal Ramaswamy, Qian Tao, Yongjun Jeff Hu, Everett A. McTeer
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Patent number: 10403630Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: GrantFiled: August 9, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D. V. Nirmal Ramaswamy
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Patent number: 10395731Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: GrantFiled: December 29, 2017Date of Patent: August 27, 2019Assignee: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Publication number: 20190067573Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.Type: ApplicationFiled: October 26, 2018Publication date: February 28, 2019Inventors: Tsz W. Chan, D. V. Nirmal Ramaswamy, Qian Tao, Yongjun Jeff Hu, Everett A. McTeer
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Patent number: 10193064Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.Type: GrantFiled: July 6, 2017Date of Patent: January 29, 2019Assignee: Micron Technology, Inc.Inventors: Tsz W. Chan, D. V. Nirmal Ramaswamy, Qian Tao, Yongjun Jeff Hu, Everett A. McTeer
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Publication number: 20190019842Abstract: Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.Type: ApplicationFiled: September 7, 2018Publication date: January 17, 2019Inventors: D.V. Nirmal Ramaswamy, Scott E. Sills, Gurtej S. Sandhu
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Publication number: 20180374870Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.Type: ApplicationFiled: August 7, 2018Publication date: December 27, 2018Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
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Publication number: 20180350824Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: ApplicationFiled: August 9, 2018Publication date: December 6, 2018Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D.V. Nirmal Ramaswamy
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Publication number: 20180342534Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.Type: ApplicationFiled: July 18, 2018Publication date: November 29, 2018Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
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Publication number: 20180342535Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.Type: ApplicationFiled: July 18, 2018Publication date: November 29, 2018Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
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Publication number: 20180342294Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
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Patent number: 10134916Abstract: A transistor device includes a pair of source/drain regions having a channel region there-between. A first gate is proximate the channel region. A gate dielectric is between the first gate and the channel region. A second gate is proximate the channel region. A programmable material is between the second gate and the channel region. The programmable material includes at least one of a) a multivalent metal oxide portion and an oxygen-containing dielectric portion, or b) a multivalent metal nitride portion and a nitrogen-containing dielectric portion. Memory cells and arrays of memory cells are disclosed.Type: GrantFiled: August 27, 2012Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
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Patent number: 10134810Abstract: Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.Type: GrantFiled: May 25, 2017Date of Patent: November 20, 2018Assignee: Micron Technology, Inc.Inventors: D.V. Nirmal Ramaswamy, Scott E. Sills, Gurtej S. Sandhu
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Patent number: 10079244Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.Type: GrantFiled: July 28, 2016Date of Patent: September 18, 2018Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu
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Patent number: 10062703Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: GrantFiled: March 15, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D. V. Nirmal Ramaswamy
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Patent number: 10062432Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.Type: GrantFiled: May 21, 2015Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
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Publication number: 20180144792Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.Type: ApplicationFiled: December 29, 2017Publication date: May 24, 2018Applicant: Micron Technology, Inc.Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
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Publication number: 20180068723Abstract: Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu