Abstract: Disclosed herein is a printed circuit board, including: a substrate; a seed layer formed on the substrate; and a circuit pattern formed on the seed layer and formed so that a diameter of an upper portion thereof and a width of a lower portion thereof are equal to each other or a diameter of the lower portion is larger than that of the upper portion. Therefore, the printed circuit board according to a preferred embodiment of the present invention forms the circuit pattern having the lower portion having the diameter larger than that of the upper portion, such that the electrical signal loss may be decreased and separation of the circuit pattern may be prevented, thereby improving whole reliability of the board.

Abstract: There is provided a method for manufacturing a printed circuit board including: preparing a substrate having a conductive layer formed on at least a portion thereof; forming an insulating layer formed with an opening through which a portion of the conductive layer is exposed on the substrate; forming a plating seed layer on the insulating layer and the exposed conductive layer; forming an electroplating layer on the plating seed layer by overplating the plating seed layer; and etching the overplated portion in a lump to form a circuit layer in the opening.

Abstract: Disclosed herein is an interposer, including: an interposer substrate configured by stacking an insulating layer of one layer or more and interlayer connected through a via; a cavity penetrating through a center of the interposer substrate in a thickness direction; and a connection electrode having a post part which is disposed on at least one of an upper surface and a lower surface of the interposer substrate, thereby increasing electrical characteristics and reducing manufacturing cost and time.

Abstract: Disclosed herein is a multi-layer type printed circuit board, including; a first insulating layer including at least one first pillar; a plurality of insulating layers laminated in a both surfaces direction of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers disposed on an outer surface of the outermost insulating layer, while contacting an outermost pillar disposed on an outermost insulating layer among the plurality of insulating layers, wherein the circuit layer and another pillar each formed in a both surfaces direction of the first insulating layer are disposed in a symmetrical form to each other based on the first insulating layer.

Abstract: Disclosed herein is a multi-layer type coreless substrate, including: a first insulating layer including at least one first pillar; a plurality of insulating layers laminated on one surface or both surfaces of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers contacting a pillar disposed on an outermost insulating layer of the plurality of insulating layers.

Abstract: Disclosed herein is a method of manufacturing a multilayer type coreless substrate, the method including: (A) preparing a carrier substrate including at least one copper foil formed on one surface or both surfaces of an insulating surface; (B) forming a coreless printed circuit precursor on one surface or both surfaces of the carrier substrate; (C) separating the carrier substrate; (D) performing a polishing cutting process on the coreless printed circuit precursor; and (E) laminating a plurality of other insulating layers on a flat outer surface of the coreless printed circuit precursor, the plurality of other insulating layers sequentially including other circuit layers and other pillars.

Abstract: Disclosed herein is a coreless substrate according to a preferred embodiment of the present invention, the coreless substrate including: a first insulating layer including at least one first pillar; a plurality of insulating layers laminated in a direction of one surface or both surfaces of the first insulating layer, including at least one circuit layer and at least one another pillar connected to the circuit layer; and a plurality of outermost circuit layers contacting an outermost pillar disposed on an outermost insulating layer among the plurality of insulating layers.