Patents by Inventor Da Huang

Da Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009345
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Patent number: 12009322
    Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.
    Type: Grant
    Filed: February 13, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Ting-Ting Kuo, Yu-Chih Huang, Chih-Wei Lin, Hsiu-Jen Lin, Chih-Hua Chen, Ming-Da Cheng, Ching-Hua Hsieh, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20240187276
    Abstract: Various arrangements for integrating control of multiple cloud-based smart-home devices are presented. Registration information may be received for a first and second smart-home device that are controlled using different cloud-based server systems. A determination may be made that that the first smart-home device and the second smart-home device share a common function. The first smart-home device and the second smart-home device may be assigned to a common operating characteristic group based on the common function being shared by the first smart-home device and the second smart-home device. A control element may be provided that allows for control of smart-home devices with the common operating characteristic group. The control element may be used to control the common function.
    Type: Application
    Filed: February 8, 2024
    Publication date: June 6, 2024
    Applicant: Google LLC
    Inventors: Benjamin Brown, Da Huang, Christopher Conover, Lisa Williams, Henry Chung
  • Publication number: 20240179948
    Abstract: An array substrate includes a planarization layer; an anode material layer on the planarization layer and in a peripheral area of the array substrate; and a plurality of gas releasing vias extending through the anode material layer configured to release gas in the planarization layer during a fabrication process. An aperture size of a first respective gas releasing via in a first region is smaller than an aperture size of a second respective gas releasing via in a second region.
    Type: Application
    Filed: July 30, 2021
    Publication date: May 30, 2024
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Da Zhou, Jianbo Wang, Taoran Zhang, Li Huang, Yang Zhou
  • Publication number: 20240175810
    Abstract: A gas sensing device for detecting a to-be-detected substance in a respiratory gas exhaled by a user includes a housing permitting entrance of the respiratory gas, and a sensing module disposed in the housing. The sensing module includes a light chamber permitting the respiratory gas to pass therethrough, a light source unit emitting light into the light chamber, first and second light sensing units outputting respectively first and second detected signals indicating first and second detected intensities respectively of first and second portions of the light whose wavelengths fall within first and second wavelength ranges, respectively, and a processing unit electrically connected to the first and second light sensing units and determining, based on the first and second detected signals, that the to-be-detected substance exists in the respiratory gas when a difference occurs in each of the first and second detected intensities over time.
    Type: Application
    Filed: May 17, 2023
    Publication date: May 30, 2024
    Inventors: Yu-Ren HUANG, Li-Yu WANG, Ming-Chun HSIAO, Chun-Han HUANG, Yu-Da CHIU
  • Publication number: 20240168371
    Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming a patterned hardmask over an underlying target layer on a substrate; and performing plasma fabrication operations in parallel on the patterned hardmask and underlying target layer in a plasma etching chamber using a plasma etch gas and a selective source gas. The plasma operations include forming a protective cap on the patterned hardmask; and removing portions of the underlying layer that are not covered by the patterned hardmask. In various embodiments, the selective source gas includes a chemical compound that includes a halogen gas that can be dissociated into a metal and a halogen, and the plasma operations include dissociating the metal and the halogen in the selective source gas and forming a protective cap on the patterned hardmask using the metal that has been dissociated.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 23, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Da Huang, Chun-Fu Kuo, Yi Hsing Yu, Li-Te Lin
  • Patent number: 11990440
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chang-Jung Hsueh, Kai-Jun Zhan, Yung-Sheng Lin
  • Publication number: 20240162095
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Inventors: Kuan-Da Huang, Hao-Heng Liu, Li-Te Lin
  • Publication number: 20240150906
    Abstract: An electrolytic cell includes a cation exchange membrane, a cathode compartment, and an anode compartment. The cathode compartment includes a gas diffusion electrode and a flow channel element, in which the flow channel element is between the cation exchange membrane and the gas diffusion electrode, and has a plurality of flow channels arranged in parallel with each other. The anode compartment includes an anode mesh, in which the cation exchange membrane is between the anode mesh and the flow channel element. A distance between the anode mesh and the gas diffusion electrode is substantially equal to the sum of a first thickness of the cation exchange membrane and a second thickness of the flow channel element. The novel electrolytic cell can combine with a chloralkali electrolytic cell to deal with gaseous CO2 and produce products, e.g., synthesis gas, for other purposes.
    Type: Application
    Filed: May 9, 2023
    Publication date: May 9, 2024
    Inventors: Hao-Ming CHEN, Tai-Lung CHEN, Wan-Tun HUNG, Yu-Cheng CHEN, Kuo-Ming HUANG, Fu-Da YEN, Che-Jui LIAO
  • Publication number: 20240153896
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20240143651
    Abstract: The present disclosure relates to the field of image definition recognition, and discloses a logging image definition recognition method and device, medium and electronic equipment. The method comprises: establishing a logging image sample library comprising a plurality of logging images; acquiring actual definition information corresponding to the respective logging images; acquiring a plurality of definitions corresponding to the respective logging images; determining target weights corresponding to the respective target image definition determination algorithms according to the plurality of definitions and the actual definition information corresponding to the respective logging images; and determining a definition of a target logging image by the respective target image definition determination algorithms and the target weights corresponding to the respective target image definition determination algorithms.
    Type: Application
    Filed: October 19, 2021
    Publication date: May 2, 2024
    Applicant: China Oilfield Services Ltd.
    Inventors: Lin Huang, Shusheng Guo, Zhenxue Hou, Chuan Fan, Danian Xu, Da Sheng, Wei Long, Guohua Zhang, Jiajie Cheng, Dong Li, Zhang Zhang, Lu Yin, Chaohua Zhang, Guibin Zhang
  • Publication number: 20240135859
    Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.
    Type: Application
    Filed: September 13, 2023
    Publication date: April 25, 2024
    Inventors: Ying-Da Chang, Chulho Choi, Yu-Chieh Huang, Ching-Chieh Wu, Hajoon Shin, Zhen-Guo Ding, Jia-Way Chen, Kyunlyeol Lee, Yongjoo Song
  • Publication number: 20240128148
    Abstract: A method includes attaching a package component to a package substrate, the package component includes: an interposer disposed over the package substrate; a first die disposed along the interposer; and a second die disposed along the interposer, the second die being laterally adjacent the first die; attaching a first thermal interface material to the first die, the first thermal interface material being composed of a first material; attaching a second thermal interface material to the second die, the second thermal interface material being composed of a second material different from the first material; and attaching a lid assembly to the package substrate, the lid assembly being further attached to the first thermal interface material and the second thermal interface material.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 18, 2024
    Inventors: Chang-Jung Hsueh, Po-Yao Lin, Hui-Min Huang, Ming-Da Cheng, Kathy Yan
  • Publication number: 20240128219
    Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 18, 2024
    Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
  • Patent number: 11961817
    Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai Jun Zhan, Chang-Jung Hsueh, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 11953738
    Abstract: The present invention discloses a display including a display panel and a light redirecting film disposed on the viewing side of the display panel. The light redirecting film comprises a light redistribution layer, and a light guide layer disposed on the light redistribution layer. The light redistribution layer includes a plurality of strip-shaped micro prisms extending along a first direction and arranged at intervals and a plurality of diffraction gratings arranged at the bottom of the intervals between the adjacent strip-shaped micro prisms, wherein each of the strip-shaped micro prisms has at least one inclined light-guide surface, and the bottom of each interval has at least one set of diffraction gratings, and the light guide layer is in contact with the strip-shaped micro prisms and the diffraction gratings.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 9, 2024
    Assignee: BenQ Materials Corporation
    Inventors: Cyun-Tai Hong, Yu-Da Chen, Hsu-Cheng Cheng, Meng-Chieh Wu, Chuen-Nan Shen, Kuo-Jung Huang, Wei-Jyun Chen, Yu-Jyuan Dai
  • Publication number: 20240112027
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing neural architecture search for machine learning models. In one aspect, a method comprises receiving training data for a machine learning, generating a plurality of candidate neural networks for performing the machine learning task, wherein each candidate neural network comprises a plurality of instances of a layer block composed of a plurality of layers, for each candidate neural network, selecting a respective type for each of the plurality of layers from a set of layer types that comprises, training the candidate neural network and evaluating performance scores for the trained candidate neural networks as applied to the machine learning task, and determining a final neural network for performing the machine learning task based at least on the performance scores for the candidate neural networks.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Inventors: Yanqi Zhou, Yanping Huang, Yifeng Lu, Andrew M. Dai, Siamak Shakeri, Zhifeng Chen, James Laudon, Quoc V. Le, Da Huang, Nan Du, David Richard So, Daiyi Peng, Yingwei Cui, Jeffrey Adgate Dean, Chang Lan
  • Publication number: 20240104872
    Abstract: Various implementations provide a view of a 3D environment including a portal for viewing a stereo item (e.g., a photo or video) positioned a distance behind the portal. One or more visual effects are provided based on texture of one or more portions of the stereo item, e.g., texture at cutoff or visible edges of the stereo item. The effects change the appearance of the stereo item or the portal itself, e.g., improving visual comfort issues by minimizing window violations or otherwise enhancing the viewing experience. Various implementations provide a view of a 3D environment including an immersive view of a stereo item without using portal. Such a visual effect may be provided to partially obscure the surrounding 3D environment.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 28, 2024
    Inventors: Bryce L. Schmidtchen, Bryan Cline, Charles O. Goddard, Michael I. Weinstein, Tsao-Wei Huang, Tobias Rick, Vedant Saran, Alexander Menzies, Alexandre Da Veiga
  • Patent number: 11942372
    Abstract: In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Da Huang, Hao-Heng Liu, Li-Te Lin
  • Publication number: 20240096787
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Ming-Da CHENG, Wei-Hung LIN, Hui-Min HUANG, Chang-Jung HSUEH, Po-Hao TSAI, Yung-Sheng LIN