Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.

Abstract: In one aspect, a system for in vivo and transcranial stimulation of brain tissue of a subject may include at least one light source, a controller to control operation of the light source, a signal detecting unit and a processor configured to receive signals from the signal detecting unit, analyze the signals and generate a feedback signal to the controller to control the light source until optimal results are obtained. In one embodiment, the light source is a laser instrument and the wavelength can range from 800 to 1100 nm. In another embodiment, the irradiance of the laser instrument can range from 50 to 1000 mW/cm2.

Abstract: A system for in vivo and transcranial stimulation of brain tissue of a subject may include at least one light source; a controller to control operation of the light source; a signal detecting unit and a processor configured to receive a signal from the signal detecting unit; analyze the signal and generate a feedback signal to the controller to control the light source until optimal results are obtained, wherein the detected signal is an electroencephalogram (EEG) signal, on which local peak frequencies are extracted and recorded periodically and repeatedly within a predetermined time frame before, during and after light stimulation, and the feedback signal is generated by comparing the local peak frequencies of before, during and after the brain stimulation to determine if brain synchronization occurs and sustains, and the feedback signal is generated.

Abstract: Various arrangements for integrating control of multiple cloud-based smart-home devices are presented. Registration information may be received for a first and second smart-home device that are controlled using different cloud-based server systems. A determination may be made that that the first smart-home device and the second smart-home device share a common function. The first smart-home device and the second smart-home device may be assigned to a common operating characteristic group based on the common function being shared by the first smart-home device and the second smart-home device. A control element may be provided that allows for control of smart-home devices with the common operating characteristic group. The control element may be used to control the common function.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming a patterned hardmask over an underlying target layer on a substrate; and performing plasma fabrication operations in parallel on the patterned hardmask and underlying target layer in a plasma etching chamber using a plasma etch gas and a selective source gas. The plasma operations include forming a protective cap on the patterned hardmask; and removing portions of the underlying layer that are not covered by the patterned hardmask. In various embodiments, the selective source gas includes a chemical compound that includes a halogen gas that can be dissociated into a metal and a halogen, and the plasma operations include dissociating the metal and the halogen in the selective source gas and forming a protective cap on the patterned hardmask using the metal that has been dissociated.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for performing neural architecture search for machine learning models. In one aspect, a method comprises receiving training data for a machine learning, generating a plurality of candidate neural networks for performing the machine learning task, wherein each candidate neural network comprises a plurality of instances of a layer block composed of a plurality of layers, for each candidate neural network, selecting a respective type for each of the plurality of layers from a set of layer types that comprises, training the candidate neural network and evaluating performance scores for the trained candidate neural networks as applied to the machine learning task, and determining a final neural network for performing the machine learning task based at least on the performance scores for the candidate neural networks.

Abstract: In some embodiments, the present disclosure relates to a method for manufacturing an integrated chip. The method includes forming a transistor structure over a substrate. The transistor structure comprises a pair of source/drain regions and a gate electrode between the source/drain regions. A lower inter-level dielectric (ILD) layer is formed over the pair of source/drain regions and around the gate electrode. A gate capping layer is formed over the gate electrode. A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer while forming a contact opening within the lower ILD layer. A lower source/drain contact is formed within the contact opening.

Abstract: Various arrangements for using captured voice to generate a custom interface controller are presented. A vocal recording from a user may be captured in which a spoken command and multiple smart-home devices are indicated. One or more common functions that map to the multiple smart-home devices may be determined. A custom interface controller may be generated that controls the one or more common functions of each smart-home device of the multiple smart-home devices.

Abstract: Nanogels and methods of synthesizing and using these nanogels are provided. The nanogels are formed by mixing a building block (e.g., polymer), crosslinker, preferably a target (e.g., biomedical compound or molecule), and a solvent in a multi-inlet vortex mixer, so as to cause the polymer and crosslinker to react and form a chemically crosslinked polymer network. In embodiments including a target, the target will be interspersed in and among that network and can be physically embedded and/or chemically bound therein.

Abstract: The present disclosure relates to a body fluid collection device (1), the body fluid collection device (1) comprises a tube body (10), wherein the tube body (10) is used to contain the collected body fluid and is provided with an opened end (12); a tube plug (20), wherein the tube plug (20) is configured to be able to hermetically close the opened end (12) of the tube body (10); and a filter (30), wherein the filter (30) is arranged in the tube body (10) for filtering out specific components from a body fluid to be collected, wherein the filter (30) is configured to be capable of being attached to the tube plug (20) at the open end, and the tube plug (20) is hermetically connected to the filter (30).

Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.

Abstract: A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.

Abstract: A method for manufacturing a semiconductor structure includes forming a semiconductor portion which has an exposed region; forming two fin sidewalls which are disposed at two opposite sides of the exposed region of the semiconductor portion, and which include a dielectric material; and performing an etching process such that the exposed region of the semiconductor portion is etched away to form a recess while a protection layer is formed to protect each of the fin sidewalls during the etching process. Other methods for manufacturing the semiconductor structure are also disclosed.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training a neural network to perform a machine learning task using a momentum and sign based optimizer.

Abstract: When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.

Abstract: In one aspect, a system for in vivo and transcranial stimulation of brain tissue of a subject may include at least one light source, a controller to control operation of the light source, a signal detecting unit and a processor configured to receive signals from the signal detecting unit, analyze the signals and generate a feedback signal to the controller to control the light source until optimal results are obtained. In one embodiment, the light source is a laser instrument and the wavelength can range from 800 to 1100 nm. In another embodiment, the irradiance of the laser instrument can range from 50 to 1000 mW/cm2.

Abstract: A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.