Abstract: An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.

Abstract: A duty cycle detection circuit may include: a timing signal generation unit to generate a plurality of timing signal groups by selectively combining multi-phase clock signals according to an enable signal; and a detection unit to generate a duty detection signal by selectively combining signals of the plurality of timing signal groups according to the enable signal.

Abstract: A duty cycle detection circuit may include a detection block configured to generate a duty detection signal by detecting a duty cycle of an input clock; and a current amount control block configured to control a current flowing through the detection block in response to the input clock, regardless of a variation in a frequency of the input clock.

Abstract: A delay locked loop (DLL) circuit may include: a DLL unit suitable for generating an internal clock by delaying an external clock by a delay amount required for locking; a single-to-differential divider suitable for generating multi-phase divided clocks at a specific edge of the internal clock; and a phase correction unit suitable for correcting a phase error between the multi-phase divided clocks.

Abstract: A latency control circuit may include a first latency control section configured to control a latency of a delay-locked termination signal according to a first divided clock signal, and generate a first preliminary signal, and a second latency control section configured to control the latency of the delay-locked termination signal according to a first divided clock bar signal which is generated by inverting the first divided clock signal, and generate a second preliminary signal. The latency control circuit may also include a signal combination unit configured to shift the first preliminary signal and the second preliminary signal by latency values set differently from each other, according to the first divided clock signal, and generate a first combined signal and a second combined signal, and a signal generation unit configured to generate a latency-controlled termination signal in response to the first combined signal and the second combined signal.

Abstract: A delay locked loop (DLL) circuit may include: an input clock control unit suitable for transmitting first and second internal clocks generated based on an external clock, and controlling transmission of the second internal clock based on a clock control signal which is activated during a predetermined period; a clock delay unit suitable for generating a first delay locked clock by delaying the first internal clock by a delay time required for locking, and generating a second delay locked clock by delaying the second internal clock based on the clock control signal; and an output clock control unit suitable for outputting the first delay locked clock and the second delay locked clock during a period in which the clock control signal is activated.

Abstract: An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.

Abstract: A regulation circuit of a semiconductor apparatus includes a control block configured to generate control signals in response to a reference clock signal and a feedback clock signal; and a noise compensation block configured to compensate for a variation in a level of power in response to the control signals.

Abstract: A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.

Abstract: An output control circuit may include a period setting signal generation unit configured to output a setup signal enabled during a designated period, in response to a delayed locked loop (DLL) locking signal and an output enable reset signal. The output control circuit may also include a clock division unit configured to divide an internal clock at a preset division ratio in response to the setup signal, and output a divided clock. In addition, the output control circuit may include a shift unit configured to shift the setup signal by a preset first time in response to the divided clock, and output a first delayed setup signal. Further, the output control circuit may include an output unit configured to receive and process the first delayed setup signal in response to the divided clock, and output the output enable reset signal.

Abstract: A latency control circuit may include a first latency control section configured to control a latency of a delay-locked termination signal according to a first divided clock signal, and generate a first preliminary signal, and a second latency control section configured to control the latency of the delay-locked termination signal according to a first divided clock bar signal which is generated by inverting the first divided clock signal, and generate a second preliminary signal. The latency control circuit may also include a signal combination unit configured to shift the first preliminary signal and the second preliminary signal by latency values set differently from each other, according to the first divided clock signal, and generate a first combined signal and a second combined signal, and a signal generation unit configured to generate a latency-controlled termination signal in response to the first combined signal and the second combined signal.