Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The method includes depositing a gate dielectric layer over the insulating layer and in the wide trench and the narrow trench using an atomic layer deposition process. The method includes forming a gate electrode layer over the gate dielectric layer. The method includes removing the gate dielectric layer and the gate electrode layer outside of the wide trench and the narrow trench.

Abstract: An optical device includes a gallium and nitrogen containing substrate comprising a surface region configured in a (20-2-1) orientation, a (30-3-1) orientation, or a (30-31) orientation, within +/?10 degrees toward c-plane and/or a-plane from the orientation. Optical devices having quantum well regions overly the surface region are also disclosed.

Abstract: A method for designing a multi-objective primer pair is disclosed. The method includes inputting a DNA template fragment, a length of a forward primer, a length of a reverse primer, at least two objectives and optimal values for each of the at least two objectives to a computer system; generating, by the computer system, a plurality of primer pairs according to the DNA template fragment, the length of the forward primer and the length of the reverse primer; and calculating, by the computer system, numerical values of the at least two objectives of each of the plurality of primer pairs and inputting the numerical values of the at least two objectives of each of the plurality of primer pairs to a Pareto Chart tool to obtain at least one primer pair, and taking the primer pair as an optimal solution of the DNA template fragment.

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

Abstract: A display device includes a plate member, an outer frame, and a display panel. The plate member has a fringe portion and a joining structure formed on the fringe portion. The fringe portion has an edge and two opposite surfaces. The outer frame has a parallel frame portion and a non-parallel frame portion extending from the parallel frame portion. The parallel frame portion is parallel to the fringe portion and is embedded into the joining structure, so as to make the outer frame and the plate member jointly from an accommodating space for accommodating the display panel. The parallel frame portion is coplanar with one of the surfaces. Therein, the joining structure can include an opening structure passing through the two surfaces and extending to the edge. Or, the joining structure can include an opening structure, passing through the two surfaces, and a raised portion.

Abstract: A display device includes a plate member, an outer frame, and a display panel. The plate member has a fringe portion and a joining structure formed on the fringe portion. The fringe portion has an edge and two opposite surfaces. The outer frame has a parallel frame portion and a non-parallel frame portion extending from the parallel frame portion. The parallel frame portion is parallel to the fringe portion and is embedded into the joining structure, so as to make the outer frame and the plate member jointly from an accommodating space for accommodating the display panel. The parallel frame portion is coplanar with one of the surfaces. Therein, the joining structure can include an opening structure passing through the two surfaces and extending to the edge. Or, the joining structure can include an opening structure, passing through the two surfaces, and a raised portion.

Abstract: A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.

Abstract: A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.

Abstract: A display device includes a frame module, a display panel, a backlight module, a rear case and a control module. The frame module includes a back plate, a frame and a fixing column. The back plate has a first surface and a second surface opposite to the first surface and a hole extending from the first surface to the second surface. The fixing column is protrudingly disposed on the frame and is coupled to the hole. The fixing column includes a pressing portion and a connecting portion connecting the frame and the pressing portion. The connecting portion is disposed in the hole, and the frame presses against the first surface, and the pressing portion presses against the second surface. The backlight module is disposed between the back plate and the display panel. The control module is disposed between the rear case and the frame module.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a test line letter structure having one or more sidewalls continuously extending along a path that defines a shape of an alpha-numeric character from a top-view. The test line letter structure is formed by forming a first polysilicon structure over a substrate and forming a second polysilicon structure over the substrate at a location laterally separated from first polysilicon structure by a dielectric layer.

Abstract: Embodiments disclosed herein relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an embodiment, a method includes conformally forming a gate dielectric layer on a fin extending from a substrate and along sidewalls of gate spacers over the fin, conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, the dummy layer as deposited comprising a dopant of fluorine, deuterium, or a combination thereof, performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer, removing the dummy layer, and forming one or more metal-containing layers over the gate dielectric layer.

Abstract: An optical device includes a gallium and nitrogen containing substrate comprising a surface region configured in a (20-2-1) orientation, a (30-3-1) orientation, or a (30-31) orientation, within +/?10 degrees toward c-plane and/or a-plane from the orientation. Optical devices having quantum well regions overly the surface region are also disclosed.

Abstract: Various examples of the present technology provide systems and methods for incorporating a switch card and adapter cards in a server system to provide flexible HDD and SSD supports. More specifically, a server system comprises a switch card having at least two different types of interfaces (e.g., a Serial Attached SCSI (SAS) interface, a serial ATA (SATA) interface, or a Peripheral Component Interconnect Express (PCIe) interface), and a controller that comprises a first Central Processing Unit (CPU) and a second CPU. The first CPU is connected to a first adapter card while the second CPU is connected to a second adapter card. The first adapter and the second adapter are coupled to the switch card of the server system.

Abstract: The present disclosure provides a system and method for providing a basic power to a system in an event that a standby power of power supply units (PSUs) of the system fails. The system comprises a plurality of active components, one or more PSUs, and a power switch. The power switch is connected to a standby power output and a main power output of the PSUs. The power switch can receive status information of the PSUs and determine whether the main power of the PSUs is within a predetermined range. In an event that the standby power of the PSUs fails and the main power of the PSUs is within the predetermined range, the power switch can switch an input power from the standby power to the main power of the PSUs and output a basic power for system use.

Abstract: A method for preparing azoxystrobin comprises the following steps: (a) mixing methyl (E)-2-[2-(6-chloropyrimidin-4-yloxy)phenyl]-3-methoxyacrylate, 2-cyanophenol, potassium carbonate, and 10-80 mol % of 1-methylpyrrolidine as a catalyst in an aprotic solvent to form a basic mixture, and reacting the basic mixture for 2-5 hrs at a temperature of 60-120° C.; and (b) subjecting the basic mixture after reaction in Step (a) to a first distillation under a reduced pressure of 80-120 torr at 70-80° C., to obtain azoxystrobin.

Abstract: A system and method to dynamically balance power to a multi-node system is disclosed. A chassis management controller is operable to regulate the power from a power source to each of the nodes. The chassis management controller determines a setting power for each nodes and a real power consumed by each node. The chassis management controller determines a next setting power for each node based on the real power and unused total power and total additional balance power for the plurality of nodes. The chassis management controller commands each node to regulate the power consumption of the node up to the setting power value.

Abstract: A process for encapsulating a bowling pin includes placing a pin in a mold; injecting a molten plastic material into the mold to encapsulate the pin; and cooling the mold to produce a finished bowling pin wherein. The plastic material includes 80% to 60% of nylon and 20% to 40% of ion resin. Preferably, the ion resin is zinc ion resin.

Abstract: The present application discloses a server system. The system includes a chassis, a motherboard installed within the chassis, and a daughterboard installed within the chassis. The motherboard includes one or more central processing unit sockets and one or more memory chip sockets. The daughterboard is communicatively connected to the motherboard. The daughterboard includes one or more input/output (I/O) connectors configured for direct external connections to outside of the chassis. The motherboard has no (I/O) connector configured for direct external connection to outside of the chassis.

Abstract: A computing device configured to detect proper cable assembly to improve assembly and problem diagnosis is provided. The computing device includes a motherboard, a function board, and a middle plane connecting the motherboard and function board. The motherboard includes a baseboard management controller (BMC). The BMC is connected to I2C buses. The function board includes integrated circuits. The middle plane includes cable connections interconnecting the I2C buses that are connected to the BMC and the integrated circuits. The integrated circuits have unique system addresses that are identifiable by the BMC.