Abstract: A method comprises forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by a trench, applying a first pre-amorphous implantation (PAI) process to the substrate and forming a first PAI region underlying the trench as a result of the first PAI process, depositing a first tensile film layer on sidewalls and a bottom of the trench, converting the first PAI region into a first dislocation plane underlying the trench using a first anneal process and forming an isolation region over the first dislocation plane.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

Abstract: A method comprises forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by a trench, applying a first pre-amorphous implantation (PAI) process to the substrate and forming a first PAI region underlying the trench as a result of the first PAI process, depositing a first tensile film layer on sidewalls and a bottom of the trench, converting the first PAI region into a first dislocation plane underlying the trench using a first anneal process and forming an isolation region over the first dislocation plane.

Abstract: A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: A device comprises a first semiconductor fin over a substrate, a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region, a first drain/source region coupled to the first semiconductor fin and the second semiconductor fin and a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin.

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract: A device comprises a first semiconductor fin over a substrate, a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region, a first drain/source region coupled to the first semiconductor fin and the second semiconductor fin and a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.

Abstract: A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.

Abstract: Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and forming a gate structure engaging the projection adjacent to the channel region, the gate structure having spaced first and second conductive layers and a strain-inducing conductive layer disposed between the first and second conductive layers. The method also includes forming epitaxial growths on portions of the projection at each side of the gate structure, the epitaxial growths imparting a first strain to the channel region, and imparting a second strain to the channel region, including performing at least one stress memorization technique on the gate structure such that the strain-inducing conductive layer imparts the second strain to the channel region, and removing the capping layer, wherein the imparting the second strain is carried out in a manner that imparts tensile strain to the channel region.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract: A semiconductor structure includes a substrate, a gate structure, and two silicon-containing structures. The substrate includes two recesses defined therein and two doping regions of a first dopant type. Each of the two doping regions extends along a bottom surface and at least portion of a sidewall of a corresponding one of the two recesses. The gate structure is over the substrate and between the two recesses. The two silicon-containing structures are of a second dopant type different from the first dopant type. Each of the two silicon-containing structures fills a corresponding one of the two recesses, and an upper portion of each of the two silicon-containing structures has a dopant concentration higher than that of a lower portion of each of the two silicon-containing structures.

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.