Patents by Inventor Da-Wen Lin
Da-Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8278179Abstract: A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET.Type: GrantFiled: March 9, 2010Date of Patent: October 2, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Da-Wen Lin, Che-Min Chu, Tsung-Hung Li, Chih-Hung Tseng, Yen-Chun Lin, Chung-Cheng Wu
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Patent number: 8278196Abstract: The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer.Type: GrantFiled: July 21, 2010Date of Patent: October 2, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, Mao-Rong Yeh, Chun Hsiung Tsai, Tsung-Hung Lee, Da-Wen Lin, Tsz-Mei Kwok
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Publication number: 20120135575Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.Type: ApplicationFiled: March 8, 2011Publication date: May 31, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: King-Yuen WONG, Ming-Lung CHENG, Chien-Tai CHAN, Da-Wen LIN, Chung-Cheng WU
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Publication number: 20120086053Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).Type: ApplicationFiled: October 8, 2010Publication date: April 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Hung TSENG, Da-Wen LIN, Chien-Tai CHAN, Chia-Pin LIN, Li-Wen WENG, An-Shen CHANG, Chung-Cheng WU
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Publication number: 20120083135Abstract: Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung TSAI, Chii-Ming WU, Da-Wen LIN
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Patent number: 8143680Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.Type: GrantFiled: May 12, 2010Date of Patent: March 27, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung, Carlos H. Diaz
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Publication number: 20120018848Abstract: The present disclosure provides a high surface dopant concentration semiconductor device and method of fabricating. In an embodiment, a method of forming the semiconductor device includes providing a substrate, forming a doped region in the substrate, forming a stressing layer over the doped region, performing a boron (B) doping implant to the stressing layer, annealing the B doping implant, and after annealing the B doping implant, forming a silicide layer over the stressing layer.Type: ApplicationFiled: July 21, 2010Publication date: January 26, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Lien Huang, Mao-Rong Yeh, Chun Hsiung Tsai, Tsung-Hung Lee, Da-Wen Lin, Tsz-Mei Kwok
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Publication number: 20110278676Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.Type: ApplicationFiled: May 14, 2010Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Lung Cheng, Yen-Chun Lin, Da-Wen Lin
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Publication number: 20110248322Abstract: An embodiment is a semiconductor device. The semiconductor device comprises a substrate, an electrode over the substrate, and a piezoelectric layer disposed between the substrate and the electrode. The piezoelectric layer causes a strain in the substrate when an electric field is generated by the electrode.Type: ApplicationFiled: April 12, 2010Publication date: October 13, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Chien-Tai Chan, Da-Wen Lin, Chung-Cheng Wu
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Publication number: 20110248351Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. An exemplary method includes providing a substrate; forming a first gate over the substrate for a first device having a first threshold voltage characteristic, the first gate including a first material having a first-type work function; forming a second gate over the substrate for a second device having a second threshold voltage characteristic that is greater than the first threshold voltage characteristic, the second gate including a second material having a second-type work function that is opposite the first-type work function; and configuring the first device and the second device as a same channel type device.Type: ApplicationFiled: April 9, 2010Publication date: October 13, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Yu Chiang, Da-Wen Lin, Shyh-Wei Wang
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Publication number: 20110223736Abstract: A method of forming a semiconductor structure includes providing a substrate including a fin at a surface of the substrate, and forming a fin field-effect transistor (FinFET), which further includes forming a gate stack on the fin; forming a thin spacer on a sidewall of the gate stack; and epitaxially growing a epitaxy region starting from the fin. After the step of epitaxially growing the epitaxy region, a main spacer is formed on an outer edge of the thin spacer. After the step of forming the main spacer, a deep source/drain implantation is performed to form a deep source/drain region for the FinFET.Type: ApplicationFiled: March 9, 2010Publication date: September 15, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Wen Lin, Che-Min Chu, Tsung-Hung Li, Chih-Hung Tseng, Yen-Chun Lin, Chung-Cheng Wu
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Publication number: 20110195555Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer.Type: ApplicationFiled: February 9, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Mao-Rong Yeh, Da-Wen Lin
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Patent number: 7994016Abstract: A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.Type: GrantFiled: November 11, 2009Date of Patent: August 9, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hsiung Tsai, Chun-Feng Nieh, Da-Wen Lin, Chien-Tai Chan
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Publication number: 20110171795Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer; and forming a fin field-effect transistor (FinFET) including implanting the semiconductor wafer using a hot-implantation to form an implanted region in the FinFET. The implanted region comprises a region selected from the group consisting essentially of a lightly doped source and drain region, a pocket region, and a deep source drain region.Type: ApplicationFiled: January 12, 2010Publication date: July 14, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Chien-Chang Su, Tsung-Hung Li, Da-Wen Lin, Wen-Sheh Huang
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Publication number: 20110127610Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.Type: ApplicationFiled: June 9, 2010Publication date: June 2, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung Ying Lee, Li-Wen Weng, Chien-Tai Chan, Da-Wen Lin, Hsien-Chin Lin
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Publication number: 20110111571Abstract: A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.Type: ApplicationFiled: November 11, 2009Publication date: May 12, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun Hsiung TSAI, Chun-Feng NIEH, Da-Wen LIN, Chien-Tai CHAN
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Publication number: 20110079820Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.Type: ApplicationFiled: October 2, 2009Publication date: April 7, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kao-Ting Lai, Da-Wen Lin, Hsien-Hsin Lin, Yuan-Ching Peng, Chi-Hsi Wu
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Publication number: 20100237441Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.Type: ApplicationFiled: May 12, 2010Publication date: September 23, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung, Carlis H. Diaz
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Patent number: 7795119Abstract: A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate.Type: GrantFiled: July 17, 2007Date of Patent: September 14, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia Ping Lo, Jerry Lai, Chii-Ming Wu, Mei-Yun Wang, Da-Wen Lin
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Patent number: 7732877Abstract: A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage.Type: GrantFiled: April 2, 2007Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Da-Wen Lin, Ying-Shiou Lin, Shyh-Wei Wang, Li-Ping Huang, Ying-Keung Leung, Carlos H. Diaz