Patents by Inventor Da-Yuan Shih

Da-Yuan Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11110534
    Abstract: In an Injection Molded Soldering system, a single, one-layer decal has one or more through hole patterns where each through hole pattern has a plurality of through holes through the decal. A drum with a drum circumference turns while the decal is forced to be adjacent to the drum circumference. The decal passes by a tangent point on the drum circumference where one or more solder-filled through hole patterns align with recessed openings on a substrate at the tangent point of the drum circumference. Applied heat causes the solder structures to melt and flow into the recessed openings.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jae-Woong Nah, Stephen L. Buchwalter, Peter A. Gruber, Da-Yuan Shih, Paul Alfred Lauro
  • Publication number: 20210229203
    Abstract: Apparatus and methods are disclosed for transferring solder to a substrate. A substrate belt moves one or more substrates in a belt direction. A decal has one or more through holes in a hole pattern that hold solder. Each of the solder holes can align with respective locations on one of the substrates. An ultrasonic head produces an ultrasonic vibration in the solder in a longitudinal direction perpendicular to the belt direction. The ultrasonic head and substrate can be moved together in the longitudinal direction to maintain the ultrasonic head in contact with the solder while the ultrasonic head applies the ultrasonic vibration. Various methods are disclosed including methods of transferring the solder with or without external heating.
    Type: Application
    Filed: January 29, 2020
    Publication date: July 29, 2021
    Inventors: Jae-Woong Nah, Stephen L. Buchwalter, Peter A. Gruber, Paul Alfred Lauro, Da-Yuan Shih
  • Publication number: 20210151402
    Abstract: Protruding solder structures are created for electrical attachment of semiconductor devices. A rigid mold having one or more mold openings is attached to and used in combination with a decal structure that has one or more decal holes. The decal structure is disposed on the rigid mold so that the decal openings are aligned over the mold openings. Each of the decal hole and mold opening in contact form a single combined volume. The single combined volumes are filled with solder to form protruding solder structures. Various structures and methods of making and using the structures are disclosed.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 20, 2021
    Inventors: Jae-Woong Nah, Stephen L. Buchwalter, Peter A. Gruber, Paul Alfred Lauro, Da-Yuan Shih
  • Patent number: 10833120
    Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobowitz, Stephen Buchwalter, Casimer DeCusatis, Peter A. Gruber, Da-Yuan Shih
  • Publication number: 20200316702
    Abstract: In an Injection Molded Soldering system, a single, one-layer decal has one or more through hole patterns where each through hole pattern has a plurality of through holes through the decal. A drum with a drum circumference turns while the decal is forced to be adjacent to the drum circumference. The decal passes by a tangent point on the drum circumference where one or more solder-filled through hole patterns align with recessed openings on a substrate at the tangent point of the drum circumference. Applied heat causes the solder structures to melt and flow into the recessed openings.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 8, 2020
    Inventors: Jae-Woong Nah, Stephen L. Buchwalter, Peter A. Gruber, Da-Yuan Shih, Paul Alfred Lauro
  • Publication number: 20200020738
    Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Lawrence Jacobowitz, Stephen Buchwalter, Casimer DeCusatis, Peter A. Gruber, Da-Yuan Shih
  • Patent number: 10490594
    Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobwitz, Stephen Buchwalter, Casimer DeCusatis, Peter A. Gruber, Da-Yuan Shih
  • Publication number: 20190326228
    Abstract: A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Chen-Hua Yu, Da-Yuan Shih
  • Patent number: 10340226
    Abstract: A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Da-Yuan Shih
  • Patent number: 10034390
    Abstract: A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Patent number: 9978709
    Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn—Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Chung-Jung Wu, Hsiao-Yun Chen, Yi-Li Hsiao, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Patent number: 9679875
    Abstract: A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: June 13, 2017
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Katsuyuki Sakuma, Da-Yuan Shih
  • Patent number: 9679882
    Abstract: A method of multi-chip wafer level packaging comprises attaching a first semiconductor die to a top side of a wafer, forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer, forming a first group of through assembly vias in the first photo-sensitive material layer, attaching a second semiconductor die to the first photo-sensitive material layer, forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer and forming a second group of through assembly vias in the second photo-sensitive material layer.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chun Hui Yu, Chen-Hua Yu, Da-Yuan Shih
  • Publication number: 20170033153
    Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Lawrence Jacobowitz, Stephen Buchwalter, Casimer DeCusatis, Peter A. Gruber, Da-Yuan Shih
  • Publication number: 20170012019
    Abstract: A method of producing a solder bump joint includes heating a solder bump comprising tin above a melting temperature of the solder bump, wherein the solder bumps comprises eutectic Sn—Bi compound, and the eutectic Sn-Bi compound is free of Ag. The method further includes stretching the solder bump to increase a height of the solder bump, wherein stretching the solder bump forms lamellar structures having a contact angle of less than 90°. The method further includes cooling down the solder bump.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Su-Chun YANG, Chung-Jung WU, Hsiao-Yun CHEN, Yi-Li HSIAO, Chih-Hang TUNG, Da-Yuan SHIH, Chen-Hua YU
  • Patent number: 9543273
    Abstract: A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Katsuyuki Sakuma, Da-Yuan Shih
  • Patent number: 9521795
    Abstract: A method includes placing a plurality of first package components over second package components, which are included in a third package component. First metal connectors in the first package components are aligned to respective second metal connectors of the second package components. After the plurality of first package components is placed, a metal-to-metal bonding is performed to bond the first metal connectors to the second metal connectors.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Da-Yuan Shih, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 9490408
    Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: November 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobowitz, Stephen Buchwalter, Casimer DeCusatis, Peter A. Gruber, Da-Yuan Shih
  • Patent number: 9475145
    Abstract: A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 25, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Chun Yang, Chung-Jung Wu, Hsiao-Yun Chen, Yi-Li Hsiao, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
  • Publication number: 20160240501
    Abstract: A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.
    Type: Application
    Filed: April 22, 2016
    Publication date: August 18, 2016
    Inventors: Peter A. Gruber, Katsuyuki Sakuma, Da-Yuan Shih