Patents by Inventor Da-Yuan Shih
Da-Yuan Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9490408Abstract: A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem. Optical alignment fiducials guide the disclosed transfer and attachment processes to achieve specified tolerances between the microoptic elements and corresponding optoelectronic devices and circuits.Type: GrantFiled: September 13, 2013Date of Patent: November 8, 2016Assignee: International Business Machines CorporationInventors: Lawrence Jacobowitz, Stephen Buchwalter, Casimer DeCusatis, Peter A. Gruber, Da-Yuan Shih
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Patent number: 9475145Abstract: A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device.Type: GrantFiled: March 14, 2013Date of Patent: October 25, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Su-Chun Yang, Chung-Jung Wu, Hsiao-Yun Chen, Yi-Li Hsiao, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
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Publication number: 20160240501Abstract: A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.Type: ApplicationFiled: April 22, 2016Publication date: August 18, 2016Inventors: Peter A. Gruber, Katsuyuki Sakuma, Da-Yuan Shih
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Patent number: 9404942Abstract: Coaxial probe structures include a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.Type: GrantFiled: February 7, 2014Date of Patent: August 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Yun-Hsin Liao, Daniel Peter Morris, Da-Yuan Shih
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Publication number: 20160211242Abstract: A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.Type: ApplicationFiled: January 19, 2015Publication date: July 21, 2016Inventors: Peter A. Gruber, Katsuyuki Sakuma, Da-Yuan Shih
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Publication number: 20160155731Abstract: A method of multi-chip wafer level packaging comprises attaching a first semiconductor die to a top side of a wafer, forming a first reconfigured wafer by embedding the first semiconductor die into a first photo-sensitive material layer, forming a first group of through assembly vias in the first photo-sensitive material layer, attaching a second semiconductor die to the first photo-sensitive material layer, forming a second photo-sensitive material layer on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer and forming a second group of through assembly vias in the second photo-sensitive material layer.Type: ApplicationFiled: February 2, 2016Publication date: June 2, 2016Inventors: Chih-Hang Tung, Chun Hui Yu, Chen-Hua Yu, Da-Yuan Shih
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Publication number: 20160143157Abstract: A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.Type: ApplicationFiled: January 22, 2016Publication date: May 19, 2016Inventors: Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
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Patent number: 9343423Abstract: A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures.Type: GrantFiled: October 28, 2014Date of Patent: May 17, 2016Assignee: International Business Machines CorporationInventors: Claudius Ferger, Michael A. Gaynes, Jae-Woong Nah, Da-Yuan Shih
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Publication number: 20160118351Abstract: A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Chen-Hua Yu, Da-Yuan Shih
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Patent number: 9305896Abstract: A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures.Type: GrantFiled: October 27, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Claudius Ferger, Michael A. Gaynes, Jae-Woong Nah, Da-Yuan Shih
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Patent number: 9263407Abstract: A method includes forming a plurality of metal posts. The plurality of metal posts is interconnected to form a metal-post row by weak portions between neighboring ones of the plurality of metal posts. The weak portions include a same metal as the plurality of metal posts. A majority of each of the plurality of metal posts is separated from respective neighboring ones of the plurality of metal posts. An end portion of each of the plurality of metal posts is plated with a metal. The plurality of metal posts is disposed into a metal post-storage. The method further includes retrieving one of the metal posts from a metal-post storage, and bonding the one of the metal posts on a metal pad.Type: GrantFiled: June 25, 2013Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Li Hsiao, Su-Chun Yang, Chih-Hang Tung, Da-Yuan Shih, Chen-Hua Yu
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Patent number: 9252120Abstract: A method of assembling a semiconductor flip chip comprising a wafer having solderable electrical conducting sites and a substrate having electrical connecting pads and electrically conductive posts operatively associated with the pads and extending away from the pads to terminate in distal ends, comprises the pre-assembly steps of solder bumping the distal ends through openings in a solder mask by injection molding solder onto the distal ends so that the distal ends extend into the mask through the openings to produce a solder bumped substrate, and soldering the solder bumped substrate to the sites.Type: GrantFiled: August 28, 2013Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Jae-Woong Nah, Da-Yuan Shih
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Patent number: 9230932Abstract: A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.Type: GrantFiled: February 9, 2012Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Da-Yuan Shih
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Patent number: 9216469Abstract: Some embodiments of the present disclosure relate to an apparatus and method to form a pattern of solder bumps. A solder paste is applied a plate comprising a pattern of holes, where each hole is partially filled by a piston attached to a movable stage. The remainder of the holes are filled by applying a force to the solder paste with a first solder paste application tool. A second solder paste application tool then removes excess paste from the front surface of the plate. The solder paste is then disposed onto a surface of a substrate by moving the movable stage, which fills a larger portion of each hole with a piston, forces the solder paste out of each hole, and forms pattern of solder paste on the surface of the substrate. The pattern of solder paste is then subjected to additional processing to form a pattern of solder bumps.Type: GrantFiled: October 18, 2013Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Li Hsiao, Da-Yuan Shih, Chih-Hang Tung, Chen-Hua Yu
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Patent number: 9082763Abstract: Disclosed embodiments include wire joints and methods of forming wire joints that can enable realization of fine pitch joints and collapse control for various packages. A first embodiment is a structure comprising a first substrate, a second substrate, and a wire joint. The first substrate comprises a first bonding surface, and the second substrate comprises a second bonding surface. The first bonding surface is opposite and faces the second bonding surface. The wire joint is attached to and between the first bonding surface and the second bonding surface.Type: GrantFiled: March 15, 2012Date of Patent: July 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Da-Yuan Shih, Chih-Hang Tung
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Patent number: 9082762Abstract: A process comprises manufacturing an electromigration-resistant under-bump metallization (UBM) flip chip structure comprising a Cu layer by applying to the Cu layer a metallic reaction barrier layer comprising NiFe. The solder employed in the flip chip structure comprise substantially lead-free tin. A structure comprises a product produced by this process. In another embodiment a process comprises manufacturing an electromigration-resistant UBM Sn-rich Pb-free solder bump flip chip structure wherein the electromigration-resistant UBM structure comprises a four-layer structure, or a three-layer structure, wherein the four layer structure is formed by providing 1) an adhesion layer, 2) a Cu seed layer for plating, 3) a reaction barrier layer, and 4) a wettable layer for joining to the solder, and the three-layer structure is formed by providing 1) an adhesion layer, 2) a reaction barrier layer, and 3) a wettable layer.Type: GrantFiled: December 28, 2009Date of Patent: July 14, 2015Assignee: International Business Machines CorporationInventors: Sung K. Kang, Paul A. Lauro, Minhua Lu, Da-Yuan Shih
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Publication number: 20150147851Abstract: A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures.Type: ApplicationFiled: October 28, 2014Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: Claudius Feger, Michael A. Gaynes, Jae-Woong Nah, Da-Yuan Shih
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Publication number: 20150147846Abstract: A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures.Type: ApplicationFiled: October 27, 2014Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: Claudius FEGER, Michael A. Gaynes, Jae-Woong Nah, Da-Yuan Shih
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Publication number: 20150108206Abstract: Some embodiments of the present disclosure relate to an apparatus and method to form a pattern of solder bumps. A solder paste is applied a plate comprising a pattern of holes, where each hole is partially filled by a piston attached to a movable stage. The remainder of the holes are filled by applying a force to the solder paste with a first solder paste application tool. A second solder paste application tool then removes excess paste from the front surface of the plate. The solder paste is then disposed onto a surface of a substrate by moving the movable stage, which fills a larger portion of each hole with a piston, forces the solder paste out of each hole, and forms pattern of solder paste on the surface of the substrate. The pattern of solder paste is then subjected to additional processing to form a pattern of solder bumps.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Li Hsiao, Da-Yuan Shih, Chih-Hang Tung, Chen-Hua Yu
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Patent number: 9012266Abstract: A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill.Type: GrantFiled: September 8, 2014Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Jae-Woong Nah, Da-Yuan Shih