Abstract: Embodiments of this specification provide a data storage method and apparatus, and a data reading method and apparatus. The data storage method is applied to a knowledge graph platform, and includes: splitting target knowledge graph data, to determine at least two pieces of to-be-stored target subgraph data, where the target knowledge graph data include a target entity node and at least one edge associated with the target entity node, and each piece of to-be-stored target subgraph data includes the target entity node and an edge with at least one target attribute; and storing the at least two pieces of to-be-stored target subgraph data in at least two consecutive data blocks based on an edge attribute, where an end entity identifier of to-be-stored target subgraph data stored in a previous data block is the same as a start entity identifier of to-be-stored target subgraph data stored in a current data block.

Abstract: Embodiments of this specification relate to a hypergraph data storage method and apparatus with a temporal characteristic and a hypergraph data query method and apparatus with a temporal characteristic. The storage method includes: obtaining raw edge data of a first hyperedge; storing first target data of the N nodes in a second storage table in a first file, and determining first storage location information of the N nodes in the second storage table; forming first hyperedge data based on the first number and the first storage location information, and storing the first hyperedge data in a first storage table in the first file; and storing the first file in a first file directory in a file system based on the first time, where the first file directory corresponds to a first time window, and the first time falls within the first time window.

Abstract: Mapping instructions included in threads to functional units of processors is disclosed. A first functional unit of a first processor may be identified that is underutilized for a first instruction included in a first thread of threads generated from a loop within source code. The first thread may be yielded to a second thread of the threads generated from the loop. A second instruction included in the second thread may be mapped to the first functional unit of the first processor.

Abstract: A technique for register renaming is disclosed. An offset retriever is configured to obtain a first offset and a second offset according to a first register usage and a second register usage, respectively, based on a thread identifier that identifies at least one of a first thread or a second thread, respectively. The first and second threads execute on a processing element (PE). An address pointer is configured to generate at least one of a first register address or a second register address based on at least one of the first offset or the second offset, respectively. The first and second register addresses correspond to first and second operands, respectively, stored in the register file. The first and second threads include first and second decoded instructions, respectively, that operate on the first and second operands, respectively.

Abstract: A technique for register renaming is disclosed. A conflict detector circuit is configured to detect a register conflict between a first decoded instruction and a second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. A mapping circuit is configured to change the first architectural register to a second architectural register and to map the second architectural register to a second physical register different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

Abstract: A system is disclosed. The system may include a processor including a register and a code memory. A reordering component may reorder a first instruction and a second instruction in a set of instructions of a first type in a list of code stored in the code memory, at least one of the first instruction and the second instruction accessing the register.

Abstract: A battery cell, a battery pack, and a power consuming device are provided. The battery cell includes a housing, an electrode core, a first current collector plate, and a conductive pillar. A first tab is arranged at an end of the electrode core in a first direction. The electrode core is arranged in the housing. The first current collector plate and the conductive pillar are arranged at an end that is of the first tab and that is away from the electrode core. The first current collector plate is constructed into a flat plate shape. The first current collector plate is electrically connected to the conductive pillar and the first tab.

Abstract: An apparatus may include at least one memory, and at least one processor configured to determine an accessibility of a first version of a page, wherein the first version of the page may be stored in the at least one memory, and perform, based on the accessibility of the first version of the page, an access of at least a portion of a second version of the page, wherein the second version of the page is stored in the at least one memory. The accessibility of the first version of the page may be based on an erase operation of the first version of the page. The access of the at least a portion of the second version of the page may include an access of a cache line of the second version of the page.

Abstract: A management technique for high bandwidth memory is disclosed. A processing management circuit (PMC) has a main executing circuit and a main memory and is configured to manage at least one processor operation performed by at least one of a first processing element (PE) or a second PE. A shared memory is configured to be shared by the PMC, the first PE, and the second PE. A memory management circuit (MMC) is configured to manage a memory operation on the shared memory based on a memory access by at least one of the PMC, the first PE, or the second PE. The at least one processor operation includes at least one of a program launch, a program execution, and an interrupt delivery.

Abstract: An apparatus may include at least one memory, and at least one processor configured to determine an accessibility of a first version of a page, wherein the first version of the page may be stored in the at least one memory, and perform, based on the accessibility of the first version of the page, an access of at least a portion of a second version of the page, wherein the second version of the page is stored in the at least one memory. The accessibility of the first version of the page may be based on an erase operation of the first version of the page. The access of the at least a portion of the second version of the page may include an access of a cache line of the second version of the page.

Abstract: Systems and methods for prefetching data are disclosed. A processor in communication with a storage device identifies a first address. The processor identifies a first setting associated with the first address. The processor issues a first command to a first storage medium of the storage device based on the first setting. The first command is for performing a first type of memory read. The storage device is configured to retrieve first data associated with the first address in the first storage medium, to a second storage medium of the storage device, based on the first command.

Abstract: The present invention relates to a method for preparing lignocellulose nanofibril and a lignocellulose nanofibril prepared by the method. The present invention also relates to a method for preparing a lignocellulose nanofibri reinforced composite material, and a lignocellulose nanofibri reinforced composite material prepared by the method.

Abstract: Systems and methods for cache management of a storage device are disclosed. The storage device is configured to receive a first code provided by a computing device; execute the first code; perform a first update of the first storage medium based on the first code; receive a second code provided by the computing device; execute the second code; and perform a second update of the first storage medium based on the second code.

Abstract: Provided are systems, methods, and apparatuses for controlling context switching based on monitoring virtualized applications. In one or more examples, the systems, devices, and methods include receiving, at a virtual machine controller and from a system profiler, a watchpoint condition; determining a number of times the watchpoint condition is detected based on implementing the watchpoint condition on an application and executing the application; determining the number of times the watchpoint condition is detected satisfies a watchpoint threshold having a value of greater than or equal to two; and based on satisfying the watchpoint threshold, pausing execution of the application and giving control of the application to the system profiler.

Abstract: Embodiments of this specification provide a data storage method and apparatus, and a data reading method and apparatus. The data storage method is applied to a knowledge graph platform, and includes: splitting target knowledge graph data, to determine at least two pieces of to-be-stored target subgraph data, where the target knowledge graph data include a target entity node and at least one edge associated with the target entity node, and each piece of to-be-stored target subgraph data includes the target entity node and an edge with at least one target attribute; and storing the at least two pieces of to-be-stored target subgraph data in at least two consecutive data blocks based on an edge attribute, where an end entity identifier of to-be-stored target subgraph data stored in a previous data block is the same as a start entity identifier of to-be-stored target subgraph data stored in a current data block.

Abstract: A system and method for debugging in hardware. In some embodiments, the system includes a processor, the processor including: a first memory configured to store an instruction; and a second memory configured to store a breakpoint bit, for the instruction, the processor being configured to: determine that the breakpoint bit is set, and based on determining that the breakpoint bit is set, to report an error.

Abstract: In some aspects, a device may include at least one circuit including an encryptor and a decryptor; memory media; and storage media, where the encryptor and decryptor are configured between the memory media and storage media; and the at least one circuit is configured to perform one or more operations including receiving at least a portion of data; encrypting, using the encryptor, the at least a portion of data as encrypted data; and storing, to the storage media, the encrypted data. In some aspects, the at least one circuit is further configured to perform one or more operations including receiving, from the storage media, the encrypted data; decrypting, using the decryptor, the encrypted data as decrypted data; and sending the decrypted data.

Abstract: Embodiments of this specification relate to a hypergraph data storage method and apparatus with a temporal characteristic and a hypergraph data query method and apparatus with a temporal characteristic. The storage method includes: obtaining raw edge data of a first hyperedge; storing first target data of the N nodes in a second storage table in a first file, and determining first storage location information of the N nodes in the second storage table; forming first hyperedge data based on the first number and the first storage location information, and storing the first hyperedge data in a first storage table in the first file; and storing the first file in a first file directory in a file system based on the first time, where the first file directory corresponds to a first time window, and the first time falls within the first time window.

Abstract: A full-hole reverse circulation cluster-type down-the-hole (DTH) hammer with multiple independent channels is provided. The DTH hammer includes a drill rod, a drill rod joint, a drill rod air pipe, a diversion chamber, at least one hammer, and an upper pressure plate, a lower pressure plate, and an upper outer hammer protection pipe for fixing the hammer, where at least one jet air pipe communicated with the diversion chamber and at least one drill cuttings discharge pipe are arranged between the hammers; lower ends of the jet air pipe and the drill cuttings discharge pipe are located close to a hammer drill bit; and the lower end of the jet air pipe is provided with jet holes for producing a negative pressure.

Abstract: A cache-coherent persistent memory (PMEM) device includes an input/output (I/O) interface; a volatile memory module; an error correction module which is configurable according to an I/O protocol; a non-volatile storage module; and at least one processor configured to: receive a store command and data corresponding to the store command from a host device through the I/O interface, based on the store command, control the volatile memory module to store the data, control the error correction module to encode the data to generate encoded data, and control the non-volatile storage module to store the encoded data.