Abstract: A method for enhancing video frame resolution according to one embodiment of the present disclosure may include loading video data including a plurality of frames having low resolution; selecting, from the group of artificial neural networks for image processing, artificial neural networks for image processing having different complexity to apply to two different frames of a video; and generating a high resolution frame by processing each frame of the video according to the selected artificial neural networks for image processing. A neural network for image processing according to one embodiment of the present disclosure may be a deep neural network generated via machine learning, and an input and output of the video may take place in an Internet of Things environment using a 5G network.

Abstract: A method for enhancing image resolution according to an embodiment of the present disclosure may include receiving a low resolution image, selecting an image processing area for the low resolution image, selecting a neural network for image processing according to an attribute of the selected area among neural network groups for image processing, and generating a high resolution image for the area by processing the selected image processing area according to the selected neural network for image processing. The neural network for image processing of the present disclosure may be a deep neural network generated through machine learning, and input and output of an image may be performed in an IoT environment using a 5G network.

Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.

Abstract: A memory device may be configured to receive a differential data strobe signal and an external data signal from outside the memory device, the memory device may include control circuitry configured to, extract a common mode of the differential data strobe signal to generate a common mode signal, generate an internal data signal based on the external data signal and the common mode signal, and generate an internal data strobe signal based on the differential data strobe signal, the internal data strobe signal associated with latching the internal data signal.

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Abstract: An embodiment of a substrate treatment device may comprise: a disk provided to be able to rotate; at least one susceptor arranged on the disk, a substrate being seated on the upper surface of the susceptor, the susceptor rotating, as the disk rotates, and revolving about the center of the disk as the axis; a metal ring coupled to the lower portion of the susceptor and arranged such that the center of the metal ring coincides with the center of the susceptor, and a magnet arranged radially on the lower portion of the disk with reference to the center of the disk and provided such that at least a part of the magnet faces the metal ring in the up/down direction.

Abstract: Described are a conductive concentrated resin composition including (a) 100 parts by weight of a base resin including 50% to 95% by weight of a polyamide resin, 2.5% to 20% by weight of a polar polymer, and 2.5% to 30% by weight of a non-polar polymer, (b) 10 parts to 40 parts by weight of a carbon nanofibril, (c) 0.5 parts to 5 parts by weight of a carbon nanoplate, and (d) 0.5 parts to 4 parts by weight of nanoclay; a conductive polyamide resin composition including the conductive concentrated resin composition; a method of preparing the conductive concentrated resin composition; and a molded article including the conductive polyamide resin composition.

Abstract: A calibration circuit includes first and second pull-up units each receiving a pull-up code and connected between a pad connected with an external resistor and a first power supply voltage, a pull-down unit connected between the pad and a second power supply voltage and receiving a pull-down code, a comparator comparing a first voltage with a reference voltage and then compare a second voltage with the reference voltage, a first digital filter adjusting the pull-up code based on a first comparison result of the first voltage with the reference voltage, and a second digital filter adjusting the pull-down code based on a second comparison result of the second voltage with the reference voltage.

Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.

Abstract: Disclosed are methods for combining a thermoplastic polymer with a carbon nanomaterial. More particularly, A method of preparing a thermoplastic polymer combined with a carbon nanomaterial includes combining the carbon nanomaterial with a pyrene derivative by stirring 1 to 40 wt % of a carbon nanomaterial, 1 to 40 wt % of a polycyclic aromatic hydrocarbon derivative, and 20 to 98 wt % of a solvent with a mechanical mixer. According to the present invention, the resulting materials exhibit excellent tensile strength, tensile modulus, electromagnetic shielding effects and anti-static effects, and the like.

Abstract: A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

Abstract: A delay-locked loop circuit includes first and second duty cycle correctors, and first and second duty cycle detectors. The first duty cycle corrector adjusts duties of some of first through fourth divided clock signals to provide first through fourth corrected clock signals, in response to a first correction code. The second duty cycle corrector adjusts delays of some of second through fourth delayed clock signals to provide first through fourth source clock signals, in response to a second correction code. The first duty cycle detector detects a duty of first propagation clock signal to generate a first sub-correction code of the first correction code, and duties of first and second recovered clock signals to generate the second correction code. The second duty cycle detector detects a duty of second propagation clock signal to generate a second sub-correction code of the first correction code.

Abstract: A calibration circuit includes first and second pull-up units each receiving a pull-up code and connected between a pad connected with an external resistor and a first power supply voltage, a pull-down unit connected between the pad and a second power supply voltage and receiving a pull-down code, a comparator comparing a first voltage with a reference voltage and then compare a second voltage with the reference voltage, a first digital filter adjusting the pull-up code based on a first comparison result of the first voltage with the reference voltage, and a second digital filter adjusting the pull-down code based on a second comparison result of the second voltage with the reference voltage.

Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.

Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.

Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

Abstract: A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.

Abstract: Provided are an electronic device and method for assisting driving of a vehicle, the electronic device including a sensor configured to sense a rotation direction of a steering wheel of the vehicle, a processor configured to monitor rotation direction switching events of the steering wheel, obtain a rotation direction switching pattern about a number of rotation direction switching events of the steering wheel per unit time, and determine whether to provide an alert to a driver of the vehicle, based on the obtained rotation direction switching pattern, and an outputter configured to output the alert to the driver, based on the determination.

Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.