Abstract: An address management method and a video apparatus using the same are provided. The address management method includes determining whether an external device is connected or not; when determining the connection to the external device, generating an invalidation message for invalidating an address; and transmitting the generated invalidation message to the external device. Accordingly, when the port connection is changed, the physical address can be correctly updated by invalidating the former physical address.

Abstract: This application relates to a novel benzo-heterocycle derivative and more particularly, it relates a composition for preventing and treating cancer or for inhibiting metastasis comprising benzo-heterocycle derivative or pharmaceutically acceptable salts thereof as an active ingredient. The present inventors confirmed that KRS has an effect on cancer metastasis by facilitating cancer (or tumor) cell migration through interaction with 67LR, and also found that a substance inhibiting the interaction between KRS and 67LR can prevent and treat cancer by inhibiting cancer cell metastasis. Accordingly, the composition of the present invention can inhibit cancer metastasis, and thus provide a novel means for prevention and treatment of cancer.

Abstract: An integrated circuit structure comprises at least one pair of complementary transistors on a substrate. The pair of complementary transistors includes a first transistor and a second transistor. In addition, only one stress-producing layer is on the first transistor and the second transistor and applies tensile strain force on the first transistor and the second transistor. The first transistor has a first channel region, a gate insulator on the first channel region, and a deuterium region between the first channel region and the gate insulator. The second transistor has a germanium doped channel region, as well as the same gate insulator on the germanium doped channel region, and the same deuterium region between the germanium doped channel region and the gate insulator.

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate.

Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

Abstract: Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

Abstract: Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material located atop the lower layer.

Abstract: Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

Abstract: Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

Abstract: A nonvolatile memory device includes a pipe gate having a pipe channel hole; a plurality of interlayer insulation layers and a plurality of gate electrodes alternately stacked over the pipe gate; a pair of columnar cell channels passing through the interlayer insulation layers and the gate electrodes and coupling a pipe channel formed in the pile channel hole; a first blocking layer and a charge trapping and charge storage layer formed on sidewalk of the columnar cell channels; and a second blocking layer formed between the first blocking layer and the plurality of gate electrodes.

Abstract: Provided are a virtualization server for presentation virtualization and a method thereof. The virtualization server includes: a virtual layer management unit which generates a virtual screen for a user terminal; a service operation unit which executes a service requested from the user terminal, and displays a result of the executed service on the virtual screen; a screen division processing unit which divides the virtual screen into a plurality of sub-blocks; and an image data encoding unit which classifies the plurality of sub-blocks into image sub-blocks and text sub-blocks and encodes the image sub-blocks by a first encoding scheme and encodes the text sub-blocks by a second encoding scheme.

Abstract: CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.

Abstract: An address management method and a device thereof are provided. The address management method includes checking by a device whether logical addresses are currently being used by external devices; and setting by the device a non-use logical address as a logical address of the device regardless of the type of the device, if the device determines that the non-use logical address exists. Therefore, a device may use all logical addresses regardless of its device type, and may also have a logical address even though all logical addresses corresponding to its device type are currently being used.

Abstract: A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.

Abstract: An output driver includes a pull-up circuit and a pull-down circuit coupled to an output terminal and a capacitor having a first terminal coupled to a gate terminal of a P-channel transistor of the pull-up circuit and a second terminal configured to receive a drive signal. The output driver further includes a drive circuit coupled to the first terminal of the capacitor and configured to transfer charge from a power supply node to the first terminal of the capacitor when the drive signal is at a signal ground voltage and to decouple the first terminal of the capacitor from the power supply node when the drive signal is at a voltage level greater than the signal ground voltage such that a voltage swing of a signal generated at the gate terminal of the P-channel transistor is constrained to be less than a voltage of the power supply node with respect to the signal ground voltage.

Abstract: An address management method and a device thereof are provided. The address management method includes determining by a device whether all logical addresses corresponding to a type of the device are currently being used by external devices; setting by the device a non-use logical address as a logical address of the device, if it is determined that one of the logical addresses is currently not in use; and setting by the device a predetermined logical address as a logical address of the device, if it is determined that all the logical addresses are currently being used. Therefore, logical addresses may be allocated to a device even if all logical addresses corresponding the type of the device are currently being used.

Abstract: An apparatus and method for transmitting and receiving multimedia broadcasting in order to provide multimedia broadcasting services and interactive broadcasting services are provided. An apparatus for receiving multimedia broadcasting includes a reference clock receiver, which receives a reference clock value, i.e., a current time value, of real-time multimedia broadcasting; a multimedia document receiver/storage, which receives and stores a first multimedia document; a media data receiver/storage, which receives and stores first media data; and a multimedia document renderer, which when the first multimedia document is scheduled at the reference clock value and the first media data is a rendering material used to render the first multimedia document, renders the first multimedia document using the first media data.

Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract: A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a different high-k metal gate stack to the planar pass gate NFET than to the planar pull-down NFET. Particularly, a threshold voltage adjustment dielectric layer, which is formed over a high-k dielectric layer, is preserved in the planar pass gate NFET and removed in the planar pull-down NFET. The combined NFET active area for the planar pass gate NFET and the planar pull-down NFET is substantially rectangular, which enables a high fidelity printing of the image of the combined NFET active area by lithographic means.

Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.