Patents by Inventor Dae Hong Min
Dae Hong Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128552Abstract: A pouch-type battery case according to an embodiment of the invention may accommodate an electrode assembly, in which electrodes and separators are alternately stacked. The pouch-type battery case may include: a pair of recess parts, each of which has a recessed shape; a pair of terraces that are disposed around the pair of recess parts and are inclined downward in a direction closer to each other in a state; in which the battery case is unfolded; and a bridge disposed between the pair of recess parts, configured to connect the pair of recess parts to each other, having a pair of connection surfaces formed to be inclined upward from a bottom surface of each of the pair of recess parts in a direction closer to each other. In the state in which the battery case is unfolded, an angle formed by the pair of terraces may be an obtuse angle.Type: ApplicationFiled: April 5, 2022Publication date: April 18, 2024Applicant: LG Energy Solution, Ltd.Inventors: Hyun Beom Kim, Min Kyu Min, Kyu Hyun Choi, Gi Man Kim, Dae Hong Kim, Se Young Oh
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Patent number: 11942567Abstract: Provided is a method of manufacturing a light-emitting element, the method including positioning a substrate, forming a first separation layer, which includes a first sacrificial layer, an etching control layer on the first sacrificial layer, and a second sacrificial layer on the etching control layer, on the substrate, forming at least one first light-emitting element on the first separation layer, and separating the first light-emitting element from the substrate.Type: GrantFiled: July 15, 2021Date of Patent: March 26, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jung Hong Min, Dae Hyun Kim, Hyun Min Cho, Jong Hyuk Kang, Dong Uk Kim, Seung A Lee, Hyun Deok Im, Hyung Rae Cha
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Publication number: 20240067535Abstract: A water purifier includes: a filter module for providing purified water by filtering raw water; a fitting valve module detachably fastened to the filter module to provide at least one of a flow path for a flow of raw water supplied to the filter module and a flow path for a flow of the purified water discharged from the filter module; and a frame including a valve support for movably supporting the fitting valve module to be movable. The fitting valve module is selectively placed in a separated state in which the fitting valve module is separated from the filter module by moving in a direction away from the filter module, or a coupled state in which the fitting valve module coupled to the filter module by moving toward the filter module.Type: ApplicationFiled: December 30, 2021Publication date: February 29, 2024Applicant: COWAY CO., LTD.Inventors: Ki Hong MIN, Man Uk PARK, Yong Yeon NOH, Dae Hwan KIM, Doo Won HAN
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Publication number: 20230378394Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.Type: ApplicationFiled: May 22, 2023Publication date: November 23, 2023Applicant: SEOUL VIOSYS CO., LTD.Inventors: Dae Hong MIN, Jun Ho YOON, Woo Cheol GWAK, Jin Woo HUH, Yong Hyun BAEK
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Publication number: 20230335673Abstract: A light emitting diode and a light emitting device having the same, in which the light emitting diode can include a first conductivity type semiconductor layer; a second conductivity type semiconductor layer; a lower active layer disposed there between; and an upper active layer disposed between the lower active layer and the second conductivity type semiconductor layer. The lower active layer can emit light having a wavelength shorter than that of the upper active layer, the upper active layer can include a plurality of well layers and a plurality of barrier layers, at least one of the plurality of barrier layers can include a first barrier layer and a second barrier layer having an n-type impurity doping concentration lower than that of the first barrier layer, and the first barrier layer can be closer to the first conductivity type semiconductor layer than the second barrier layer.Type: ApplicationFiled: March 10, 2023Publication date: October 19, 2023Applicant: SEOUL VIOSYS CO., LTD.Inventors: Dae Hong MIN, Yong Hyun BAEK, Ji Hun KANG
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Publication number: 20230215846Abstract: A light emitting device according to an exemplary embodiment includes a first light emission region and a second light emission region. The first and second light emission regions include a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active region formed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, an area of the first light emission region is larger than an area of the second emission region, and at least one of the first emission region or the second emission region emits light of a plurality of peak wavelengths.Type: ApplicationFiled: December 26, 2022Publication date: July 6, 2023Applicant: SEOUL VIOSYS CO., LTD.Inventors: Dae Hong MIN, Yong Hyun BAEK, Ji Hun KANG, Chung Hoon LEE
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Patent number: 11658264Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.Type: GrantFiled: September 18, 2020Date of Patent: May 23, 2023Assignee: Seoul Viosys Co., Ltd.Inventors: Dae Hong Min, Jun Ho Yoon, Woo Cheol Gwak, Jin Woo Huh, Yong Hyun Baek
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Publication number: 20230098895Abstract: A light emitting diode according to an exemplary embodiment of the present disclosure includes: a first conductivity type nitride semiconductor layer; a V-pit generation layer disposed on the n-type nitride semiconductor layer and having a V-pit; a lower active layer disposed on the V-pit generation layer; an upper active layer disposed on the lower active layer; an intermediate layer disposed between the lower active layer and the upper active layer; a second conductivity type nitride semiconductor layer disposed on the upper active layer, an upper step coverage layer disposed between the second conductivity type semiconductor layer and the upper active layer; and a lower step coverage layer disposed between the intermediate layer and the lower active layer, in which in an electroluminescence spectrum, the light emitting diode emits light having a highest peak intensity in a wavelength range of 500 nm or more in a visible light region.Type: ApplicationFiled: December 8, 2022Publication date: March 30, 2023Inventors: Dae Hong MIN, Yong Hyun BAEK, Ji Hun KANG
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Publication number: 20230093367Abstract: A light emitting device and a light emitting module having the same are provided. A light emitting device includes: a first conductivity type semiconductor layer; a second conductivity type semiconductor layer; and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, in which, upon operation, the active layer emits light of a first peak wavelength and light of a second peak wavelength in which the first peak wavelength may be within a range of about 400 nm to about 415 nm, and the second peak wavelength may be greater than or equal to about 440 nm.Type: ApplicationFiled: November 29, 2022Publication date: March 23, 2023Applicant: SEOUL VIOSYS CO., LTD.Inventors: Yong Hyun BAEK, Dae Hong MIN, Ji Hun KANG, Chung Hoon LEE
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Publication number: 20230076963Abstract: A light emitting diode according to an exemplary embodiment of the present disclosure includes: a first conductivity type nitride semiconductor layer; a V-pit generation layer disposed on the n-type nitride semiconductor layer and having a V-pit; a lower active layer disposed on the V-pit generation layer; an upper active layer disposed on the lower active layer; an intermediate layer disposed between the lower active layer and the upper active layer; and a second conductivity type nitride semiconductor layer disposed on the upper active layer, in which the lower active layer and the upper active layer emit light having different peak wavelengths from each other.Type: ApplicationFiled: August 22, 2022Publication date: March 9, 2023Inventors: Dae Hong MIN, Yong Hyun BAEK, Ji Hun KANG
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Publication number: 20230011795Abstract: A multi-band light emitting diode is provided. The multi-band light emitting diode includes a first conductivity type semiconductor layer, a V-pit generation layer disposed on the first conductivity type semiconductor layer and having a first V-pit of a first inlet width, a stress relief layer disposed on the V-pit generation layer and providing a second V-pit of a second inlet width greater than the first inlet width of the V-pit on the first V-pit, an active layer disposed on the stress relief layer and including a first active layer region formed on a flat surface of the stress relief layer and a second active layer region formed in the second V-pit, and a second conductivity type semiconductor layer disposed on the active layer.Type: ApplicationFiled: June 29, 2022Publication date: January 12, 2023Applicant: SEOUL VIOSYS CO., LTD.Inventors: Dae Hong MIN, Yong Hyun BAEK, Ji Hun KANG
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Publication number: 20220367752Abstract: A light emitting diode includes a first conductivity type nitride semiconductor layer, a V-pit generation layer disposed on the first conductivity type nitride semiconductor layer and having V-pits, an active layer disposed on the V-pit generation layer, a stress relief layer disposed between the V-pit generation layer and the active layer, and a second conductivity type nitride semiconductor layer disposed on the active layer. The stress relief layer and the active layer may be formed in the V-pits, as well as on a flat surface of the V-pit generation layer, and the active layer may emit light of a multi-band spectrum.Type: ApplicationFiled: May 10, 2022Publication date: November 17, 2022Applicant: SEOUL VIOSYS CO., LTD.Inventors: Dae Hong MIN, Yong Hyun BAEK, Ji Hun KANG
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Publication number: 20220285579Abstract: A light emitting diode according to an exemplary embodiment of the present disclosure includes an n-type nitride semiconductor layer, a V-pit generation layer, a sub-emission layer, an active layer, and a p-type nitride semiconductor layer. The sub-emission layer is disposed on the n-type nitride semiconductor layer and having V-pits. The active layer is disposed on the sub-emission layer and having a first well region formed along a flat surface of the V-pit generation layer and a second well region formed in the V-pit of the V-pit generation layer. The p-type nitride semiconductor layer is disposed on the active layer. An energy band gap of the sub-emission layer is wider than that of the first well region of the active layer. The light emitting diode emits light having at least three different peak wavelengths at a single chip level.Type: ApplicationFiled: February 28, 2022Publication date: September 8, 2022Applicant: SEOUL VIOSYS CO., LTD.Inventors: Yong Hyun BAEK, Dae Hong MIN, Ji Hun KANG
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Publication number: 20220262983Abstract: A light emitting diode includes an n-type nitride semiconductor layer, a V-pit generation layer disposed on the n-type nitride semiconductor layer and having V-pits, an active layer disposed on the V-pit generation layer and including a first well region formed along a flat surface of the V-pit generation layer and a second well region formed in the V-pit of the V-pit generation layer, a p-type nitride semiconductor layer disposed on the active layer and a sub-emission layer interposed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer and disposed near the active layer. The sub-emission layer may emit light having a peak wavelength within a range of wavelengths shorter than a peak wavelength of the first well region, and light emitted from the light emitting diode is within a range of 0.205?X?0.495 and 0.265?Y?0.450 in CIE color coordinates (X, Y).Type: ApplicationFiled: February 16, 2022Publication date: August 18, 2022Applicant: SEOUL VIOSYS CO., LTD.Inventors: Chung Hoon LEE, Yong Hyun BAEK, Ji Hun KANG, Dae Hong MIN, Dae Sung CHO, So Ra LEE
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Publication number: 20220216188Abstract: A light emitting device and a light emitting module having the same are provided. The light emitting module includes a circuit board and a plurality of light emitting units arranged on the circuit board. Each of the plurality of light emitting units includes a light emitting device. The plurality of light emitting units emits light of different colors from one another.Type: ApplicationFiled: January 5, 2022Publication date: July 7, 2022Applicant: SEOUL VIOSYS CO., LTD.Inventors: Yong Hyun BAEK, Dae Hong MIN, Ji Hun KANG, Chung Hoon LEE
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Publication number: 20210074883Abstract: A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.Type: ApplicationFiled: September 18, 2020Publication date: March 11, 2021Applicant: SEOUL VIOSYS CO., LTD.Inventors: Dae Hong MIN, Jun Ho YOON, Woo Cheol GWAK, Jin Woo HUH, Yong Hyun BAEK
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Patent number: 8048800Abstract: A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method.Type: GrantFiled: October 22, 2009Date of Patent: November 1, 2011Assignee: Dongguk University Industry—Academic Corporation FoundationInventors: Jin-Koo Rhee, Seong-Dae Lee, Mi-Ra Kim, Dae-Hong Min, Wan-Joo Kim
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Publication number: 20110059609Abstract: A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method.Type: ApplicationFiled: October 22, 2009Publication date: March 10, 2011Applicant: Dongguk University Industry-Academic Cooperation FoundationInventors: Jin-Koo Rhee, Seong-Dae Lee, Mi-Ra Kim, Dae-Hong Min
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Publication number: 20090321798Abstract: Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG layer formed on the scribe area; forming a SiN layer on the entire surface of the semiconductor substrate; masking the cell area, and then removing the SiN layer formed on the scribe area; forming a second USG layer on the entire surface of the semiconductor substrate; and masking the scribe area, and then removing the second USG layer formed on the cell area. The USG layer is only formed on the scribe layer without the SiN layer, so that SiN particles do not drop onto the USG layer during the sintering process.Type: ApplicationFiled: September 3, 2009Publication date: December 31, 2009Inventor: Dae Hong MIN
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Patent number: 7605016Abstract: Disclosed are a CMOS sensor and a method of fabricating the CMOS sensor. The method includes the steps of: forming a first USG layer on an entire surface of a semiconductor substrate including a cell area and a scribe area; masking the cell area, and then removing the first USG layer formed on the scribe area; forming a SiN layer on the entire surface of the semiconductor substrate; masking the cell area, and then removing the SiN layer formed on the scribe area; forming a second USG layer on the entire surface of the semiconductor substrate; and masking the scribe area, and then removing the second USG layer formed on the cell area. The USG layer is only formed on the scribe layer without the SiN layer, so that SiN particles do not drop onto the USG layer during the sintering process.Type: GrantFiled: December 27, 2006Date of Patent: October 20, 2009Assignee: Dongbu Electronics Co., Ltd.Inventor: Dae Hong Min