Abstract: A clock generator including a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals; a loop filter configured to generate a first control voltage signal based on the detection signal; a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal, a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal, and a second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal is provided.

Abstract: A data backup method for performing a post package repair (PPR) operation includes reading repair unit information of a memory device, storing the repair unit information in a register, determining whether to perform the PPR operation in response to a read error occurring while the memory device is being accessed, and performing a data backup operation of the memory device based on the repair unit information in response to determining that the PPR operation is to be performed.

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Abstract: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Abstract: A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.

Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Abstract: A semiconductor memory device includes: a normal memory cell block including a first plurality of memory cells; a redundancy memory cell block including a second plurality of memory cells and configured for use in replacing memory cells of the normal memory cell block; a weak cell information storage configured to store information regarding weak memory cells in the normal and redundancy memory cell blocks; and a refresh control circuit configured to control a refresh rate of memory cells in the normal and redundancy memory cell blocks based on the information regarding weak memory cells in the weak cell information storage. The weak memory cells in the normal and redundancy memory cell blocks are refreshed at least once more than other memory cells in the normal and redundancy memory cell blocks during a refresh cycle.

Abstract: A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.

Abstract: A magnetic random access memory (MRAM) includes a memory cell having a first transistor and a first magnetic tunneling junction (MTJ) layer, and a reference cell operable as a basis when reading data stored in the memory cell, the reference cell including second and third MTJ layers arranged in parallel to each other, and a second transistor connected in series to each of the second and third MTJ layers, the second transistor having a driving capability corresponding to twice a driving capability of the first transistor of the memory cell.

Abstract: A method of fabricating a liquid crystal display device includes: providing first and second substrates having a plurality of unit cell regions; forming a plurality of main seal patterns on the first substrate, each main seal pattern having an injection; forming an auxiliary seal pattern on the first substrate, the auxiliary seal pattern surrounding the plurality of main seal patterns and having at least one open portion; attaching the first substrate to the second substrate; providing an adhesive at the at least one open portion; and etching the first and second substrates, wherein a viscosity of the adhesive is within a range of about 5 to 100 centipoises (cP).

Abstract: A cassette capable of preventing breakage in glass substrates includes lower and upper frames; side frames between the lower and upper frames for connecting the lower and upper frames to each other, the side frames having a plurality of insertion recesses for receiving glass substrates; and a stopper at the rear of the cassette for preventing the glass substrates from exiting a rear portion of the cassette, wherein the stopper formed with a buffer covering material.

Abstract: A method for repairing a substrate includes injecting a restoration material onto a substrate including a defect, the restoration material covering the defect; hardening the restoration material; and abrading the hardened restoration material such that the hardened restoration material and the substrate form a flat top surface.

Abstract: A magnetic random access memory (MRAM) includes a memory cell having a first transistor and a first magnetic tunneling junction (MTJ) layer, and a reference cell operable as a basis when reading data stored in the memory cell, the reference cell including second and third MTJ layers arranged in parallel to each other, and a second transistor connected in series to each of the second and third MTJ layers, the second transistor having a driving capability corresponding to twice a driving capability of the first transistor of the memory cell.

Abstract: An upgradable SMART (Self-Monitoring Analysis and Reporting Technology) battery pack capable of upgrading a SMART function thereof is provided, including a battery array, a host interface for supplying power to a host and performing a SMART communication therewith, a protection circuit for protecting battery cells in the battery array from overcurrent or overvoltage, a microprocessor for monitoring a current state of the battery array, calculating a battery capacity thereof and controlling the SMART communication with the host via the host interface, a nonvolatile memory for storing an operational program of the microprocessor and battery information, a signal processor for converting a level of a signal to be sent to the host via the host interface into a predetermined level that is desired by the host and processing the level-converted signal, and an input/output port for performing an interfacing operation between the host and the microprocessor to download a control program and data from the host.

Abstract: In a magnetic random access memory (MRAM), and a method of reading data from the same, the MRAM includes a memory cell having one transistor and one magnetic tunneling junction (MTJ) layer, and a reference cell that is operable for use as a basis when reading data stored in the memory cell, wherein the reference cell includes first and second MTJ layers provided in parallel to each other, and first and second transistors provided in parallel to each other, the first and second transistors being respectively connected in series to the first and second MTJ layers. Alternatively, one transistor having a driving capability corresponding to twice a driving capability of the transistor of the memory cell may be substituted for the first and second transistors of the reference cell.

Abstract: A cassette capable of preventing breakage in glass substrates includes lower and upper frames; side frames between the lower and upper frames for connecting the lower and upper frames to each other, the side frames having a plurality of insertion recesses for receiving glass substrates; and a stopper a the rear of the cassette for preventing the glass substrates from exiting a rear portion of the cassette, wherein the stopper formed with a buffer covering material.

Abstract: Herein disclosed is an upgradable SMART (Self-Monitoring Analysis and Reporting Technology) battery pack which is capable of upgrading a SMART function thereof. The upgradable SMART battery pack comprises a battery array, a host interface for supplying power to a host and performing a SMART communication therewith, a protection circuit for protecting battery cells in the battery array from overcurrent or overvoltage, a microprocessor for monitoring a current state of the battery array, calculating a battery capacity thereof and controlling the SMART communication with the host via the host interface, a nonvolatile memory for storing a program necessary to an operation of the microprocessor and unique battery information, and a signal processor for converting a level of a signal to be sent to the host via the host interface into that desired by the host and processing the level-converted signal.

Abstract: A method of fabricating a liquid crystal display device includes: providing first and second substrates having a plurality of unit cell regions; forming a plurality of main seal patterns on the first substrate, each main seal pattern having an injection; forming an auxiliary seal pattern on the first substrate, the auxiliary seal pattern surrounding the plurality of main seal patterns and having at least one open portion; attaching the first substrate to the second substrate; providing an adhesive at the at least one open portion; and etching the first and second substrates, wherein a viscosity of the adhesive is within a range of about 5 to 100 centipoises (cP).