Patents by Inventor Dae-Kun Yoon

Dae-Kun Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7863955
    Abstract: A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: January 4, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dae-Han Kwon, Kyung-Hoon Kim, Dae-Kun Yoon, Taek-Sang Song
  • Patent number: 7855933
    Abstract: A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: December 21, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon, Dae-Kun Yoon
  • Patent number: 7839196
    Abstract: A multi-phase clock generation circuit having a low skew imprecision is presented. The circuit includes a phase clock generation block and a phase correction block. The phase clock generation block is configured to generate a plurality of phase clocks having phases different from each other with response to a pair of input clocks. The phase correction block is configured to generate final output interpolated phase clocks in which each has a center phase by adjusted by multiple phase clocks that have adjacent phases.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: November 23, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae Kun Yoon
  • Patent number: 7825712
    Abstract: A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently controlled. The multi-phase clock signals are out of phase with each other. A clock control block is configured to produce output multi-clock signals by selectively outputting one among the interpolated phase clock signal groups using a digital control signal having a plurality of bits which are produced based on phase differences of the multi-phase clock signals.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: November 2, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae Kun Yoon
  • Patent number: 7812650
    Abstract: Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: October 12, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon, Dae-Kun Yoon
  • Patent number: 7791391
    Abstract: A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out, N-bit code values are stored according to a plurality of detected phase differences. A controller shares the N-bit code counter, controls the generation of the N-bit code values according to the plurality of detected phase differences, and controls the storing of the N-bit code values in an allocated space of the storage by use of a multiplexer configured to provide the plurality of detected phase differences to the N-bit code counter, and a demultiplexer configured to store the N-bit code values in the allocated space of the storage.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: September 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dae-Kun Yoon, Dae-Han Kwon, Taek-Sang Song
  • Publication number: 20100148842
    Abstract: A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently controlled. The multi-phase clock signals are out of phase with each other. A clock control block is configured to produce output multi-clock signals by selectively outputting one among the interpolated phase clock signal groups using a digital control signal having a plurality of bits which are produced based on phase differences of the multi-phase clock signals.
    Type: Application
    Filed: March 19, 2009
    Publication date: June 17, 2010
    Inventor: Dae Kun Yoon
  • Patent number: 7738621
    Abstract: A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 15, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dae-Kun Yoon, Kyung-Hoon Kim, Dae-Han Kwon, Taek-Sang Song
  • Publication number: 20100117692
    Abstract: A multi-phase clock generation circuit having a low skew imprecision is presented. The circuit includes a phase clock generation block and a phase correction block. The phase clock generation block is configured to generate a plurality of phase clocks having phases different from each other with response to a pair of input clocks. The phase correction block is configured to generate final output interpolated phase clocks in which each has a center phase by adjusted by multiple phase clocks that have adjacent phases.
    Type: Application
    Filed: December 23, 2008
    Publication date: May 13, 2010
    Inventor: Dae Kun YOON
  • Patent number: 7701267
    Abstract: A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: April 20, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Dae-Kun Yoon, Dae-Han Kwon, Chang-Kyu Choi, Jun-Woo Lee
  • Publication number: 20090322394
    Abstract: A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.
    Type: Application
    Filed: November 7, 2008
    Publication date: December 31, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Taek-Sang SONG, Dae-Han Kwon, Dae-Kun Yoon
  • Publication number: 20090278577
    Abstract: A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal.
    Type: Application
    Filed: June 30, 2008
    Publication date: November 12, 2009
    Inventors: Dae-Kun Yoon, Dae-Han Kwon, Chang-Kyu Choi, Jun-Woo Lee
  • Patent number: 7612593
    Abstract: Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 3, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyung-Hoon Kim, Jun-Woo Lee, Dae-Kun Yoon, Taek-Sang Song
  • Publication number: 20090256610
    Abstract: A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out; a storage configured to store N-bit code values according to a plurality of detected phase differences; and a controller configured to share the N-bit code counter, control the generation of the N-bit code values according to the plurality of detected phase differences, and control the storing of the N-bit code values in an allocated space of the storage.
    Type: Application
    Filed: June 30, 2008
    Publication date: October 15, 2009
    Inventors: Dae-Kun Yoon, Dae-Han Kwon, Taek-Sang Song
  • Publication number: 20090168944
    Abstract: A low pass filter includes a driver unit configured to output a voltage proportional to an input pulse width, a charge/discharge unit configured to charge the output voltage of the driver unit, a comparator unit configured to compare an output voltage of the charge/discharge unit with a reference value to output a square wave signal, and a switching unit configured to switch the charge/discharge unit to an operation state, based on a bandwidth expansion signal.
    Type: Application
    Filed: December 28, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon, Dae-Kun Yoon
  • Publication number: 20090168552
    Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.
    Type: Application
    Filed: May 1, 2008
    Publication date: July 2, 2009
    Inventors: Dae-Kun Yoon, Dae-Han Kwon, Taek-Sang Song
  • Publication number: 20090160510
    Abstract: Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.
    Type: Application
    Filed: June 9, 2008
    Publication date: June 25, 2009
    Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon, Dae-Kun Yoon
  • Publication number: 20090128208
    Abstract: Apparatus for detecting duty ratio of signals in semiconductor device circuit includes a circuit for detecting a duty ratio of signals in a semiconductor device includes a comparing unit which compares a duty cycle of first and second input clock signals input differentially and generates a first output signal and a second output signal, a latching unit which stores the first and second output signals and generates a detected signal corresponding to the first and second output signals, and an adjusting unit which receives the first and the second output signals, and transmits the first and the second output signals to the latching unit based on a voltage level difference of the first and second output signals.
    Type: Application
    Filed: November 3, 2008
    Publication date: May 21, 2009
    Inventors: Taek-Sang Song, Kyung-Hoon Kim, Dae-Han Kwon, Dae-Kun Yoon
  • Publication number: 20090115459
    Abstract: A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal.
    Type: Application
    Filed: December 27, 2007
    Publication date: May 7, 2009
    Inventors: Dae-Han Kwon, Kyung-Hoon Kim, Dae-Kun Yoon, Taek-Sang Song
  • Publication number: 20090115467
    Abstract: A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.
    Type: Application
    Filed: December 27, 2007
    Publication date: May 7, 2009
    Inventors: Dae-Han Kwon, Kyung-Hoon Kim, Dae-Kun Yoon, Taek-Sang Song