Abstract: Disclosed herein are a data driving device and a display device using the same. The data driving device includes a selector for sequentially selecting pieces of gamma reference data input from banks in the order of a first color, a second color, and a third color, and a voltage output part for converting the pieces of gamma reference data for each color, which is sequentially input, into gamma reference voltages.

Abstract: A data driving circuit includes a first voltage divider circuit configured to output a gamma compensation voltage for a first color, a second voltage divider circuit configured to output a gamma compensation voltage for a second color, a third voltage divider circuit configured to output a gamma compensation voltage for a third color, a first digital-to-analog converter (DAC) configured to convert input data for the first color using the gamma compensation voltage for the first color to output a data voltage of a first channel, a second DAC configured to convert input data for the second color using the gamma compensation voltage for the second color to output a data voltage of a second channel, and a third DAC configured to convert input data for the third color using the gamma compensation voltage for the third color to output a data voltage of a third channel.

Abstract: A storage device having an improved operation speed includes memory blocks and a sudden power-off manager. The memory blocks connected to word lines as part of a super block. The sudden power-off manager in communication with the memory blocks and configured to, in response to a sudden power off, 1) select reference word lines among the word lines to group the word lines into word line zones defined using the reference word lines, 2) perform read operations on pages connected to the reference word lines to determine states of the pages connected to the reference word lines, 3) select a first erase page search zone among the word line zones based on results of the read operations, and 4) determine a first erase page located at a boundary between a program page and an erase page in the first erase page search zone.

Abstract: A display device includes a timing controlling part generating an image data, a data control signal and a gate control signal; a data driving part generating a data voltage using the image data and the data control signal; a gate driving part generating a gate voltage using the gate control signal; a display panel including a plurality of subpixels and displaying an image using the data voltage and the gate voltage; and a plurality of first MUX switches and a plurality of second MUX switches sequentially transmitting the data voltage to two of a same color among the plurality of subpixels.

Abstract: A display device includes: a timing controlling part generating an image data, a data control signal and a gate control signal; a data driving part generating a data voltage using the image data and the data control signal; a gamma part transmitting the data voltage corresponding to the image data; a gate driving part generating a gate voltage using the gate control signal; a display panel including subpixels, gate lines, left data lines at a left side of the subpixels and right data lines at a right side of the subpixels; and first MUX switches, second MUX switches, third MUX switches, fourth MUX switches, fifth MUX switches and sixth MUX switches sequentially transmitting the data voltage to the left data lines and the right data lines.

Abstract: A nonvolatile memory device includes a peripheral logic structure including a peripheral circuit on a substrate, a horizontal semiconductor layer extending along an upper surface of the peripheral logic structure, stacked structures arranged in a first direction on the horizontal semiconductor layer and including interlayer insulating films and conductive films alternately stacked in a direction perpendicular to the substrate, a first opening disposed between the stacked structures and included in the horizontal semiconductor layer to expose a part of the peripheral logic structure and a second opening arranged in a second direction, which differs from the first direction, from the first opening, included in the horizontal semiconductor layer, and disposed adjacent to the first opening. The peripheral logic structure includes a control transistor overlapping the second opening in a plan view and controlling operation of the plurality of stacked structures.

Abstract: Multi-state switchability is highly desirable in optoelectronic devices. For liquid crystal (LC) based devices, the stability of any configuration is achieved through a balance between imposed interactions and the LC's orientational elasticity. In most cases, the latter acts to resist deformation. By combining surface topography and chemical patterning, provided here are the effects of saddle-splay orientational elasticity, a property that, despite being intrinsic to all LCs, is routinely suppressed. Utilizing theory and continuum elastic calculations, provided here are example conditions for which, even using generic, achiral LC materials, spontaneously broken surface symmetries develop. Also provided are multi-stable devices in which a weak, but directional, applied field switches between spontaneously-polar surface state domains. The disclosed approach is useful in low-field and fast-switching optoelectronic devices, beyond those attainable by current technologies.

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Abstract: A semiconductor memory device includes a mold structure including gate electrodes stacked on a first substrate, a channel structure that penetrates a first region of the mold structure to cross the gate electrodes, a first through structure that penetrates a second region of the mold structure, and a second through structure that penetrates a third region of the mold structure. The mold structure further includes memory cell blocks extending in a first direction and spaced apart in a second direction, and a dummy block extending in the first direction and disposed between the memory cell blocks. Each of the memory cell blocks and the dummy block includes a cell region and an extension region arranged in the first direction. The first region is the cell region of one of the memory cell blocks, the second region is the extension region of the one of the memory cell blocks, and the third region is the extension region of the dummy block.

Abstract: A storage device including, a plurality of non-volatile memories configured to include a memory cell region including at least one first metal pad; and a peripheral circuit region including at least one second metal pad and vertically connected to the memory cell region by the at least one first metal pad and the at least one second metal pad, and a controller connected to the plurality of non-volatile memories through a plurality of channels and configured to control the plurality of non-volatile memories, wherein the controller selects one of a first read operation mode and a second read operation mode and transfers a read command corresponding to the selected read operation mode to the plurality of non-volatile memories, wherein one sensing operation is performed to identify one program state among program sates in the first read operation mode, and wherein at least two sensing operations are performed to identify the one program state among the program states in the second read operation mode.

Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sens

Abstract: Disclosed herein are a data driving device and a display device using the same. The data driving device includes a selector for sequentially selecting pieces of gamma reference data input from banks in the order of a first color, a second color, and a third color, and a voltage output part for converting the pieces of gamma reference data for each color, which is sequentially input, into gamma reference voltages.

Abstract: A vehicle includes: a camera obtaining an external view of the vehicle and acquiring illuminance data; a radar detecting a target object located outside the vehicle and acquiring radar data; and a controller including at least one processor for processing the illuminance data acquired by the camera and the radar data acquired by the radar.

Abstract: The present disclosure relates to a vehicle and a method of controlling the same, and more particularly, to a technique of increasing a reliability of a collision avoidance control system by performing a vehicle front collision determination and a vehicle side collision determination by different controllers.

Abstract: Disclosed herein is a display which activates a maximum screen which is an entirety of a screen of a flexible display panel to display an image thereon in an unfolded state of the flexible display panel and activates a part of the screen in a folded state of the flexible display panel so that the activated screen that is smaller than the maximum screen displays the image and a deactivated screen displays black.

Abstract: A storage device having an improved operation speed includes memory blocks and a sudden power-off manger. The memory blocks connected to word lines as part of a super block. The sudden power-off manager in communication with the memory blocks and configured to, in response to a sudden power off, 1) select reference word lines among the word lines to group the word lines into word line zones defined using the reference word lines, 2) perform read operations on pages connected to the reference word lines to determine states of the pages connected to the reference word lines, 3) select a first erase page search zone among the word line zones based on results of the read operations, and 4) determine a first erase page located at a boundary between a program page and an erase page in the first erase page search zone.

Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sens

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, an input/output circuit, a sensing line, and a detecting circuit. The first semiconductor chip includes bitlines, wordlines, first bonding pads electrically connected to the bitlines, second bonding pads electrically connected to the wordlines, and memory cells electrically connected to the bitlines and the wordlines. The second semiconductor chip includes third bonding pads that are electrically connected to the first bonding pads and fourth bonding pads that are electrically connected to the second bonding pads. The input/output circuit writes data to the memory cells via the third bonding pads. The sensing line extends along edge portions of at least one of the first and second semiconductor chips. The detecting circuit is in the second semiconductor chip and can detect defects from at least one of the first and second semiconductor chips using the sensing line.

Abstract: A nonvolatile memory device with high security is provided.

Abstract: A data driving circuit includes a first voltage divider circuit configured to output a gamma compensation voltage for a first color, a second voltage divider circuit configured to output a gamma compensation voltage for a second color, a third voltage divider circuit configured to output a gamma compensation voltage for a third color, a first digital-to-analog converter (DAC) configured to convert input data for the first color using the gamma compensation voltage for the first color to output a data voltage of a first channel, a second DAC configured to convert input data for the second color using the gamma compensation voltage for the second color to output a data voltage of a second channel, and a third DAC configured to convert input data for the third color using the gamma compensation voltage for the third color to output a data voltage of a third channel.