Patents by Inventor Dae-Seong LEE
Dae-Seong LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10673420Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.Type: GrantFiled: May 16, 2018Date of Patent: June 2, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun Lee, Dae Seong Lee, Minsu Kim, Ahreum Kim, Chunghee Kim
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Publication number: 20200144267Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.Type: ApplicationFiled: January 3, 2020Publication date: May 7, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Dae Seong LEE, Min Su KIM
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Patent number: 10587249Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.Type: GrantFiled: May 14, 2019Date of Patent: March 10, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Su Kim, Dae Seong Lee
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Patent number: 10553585Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.Type: GrantFiled: August 9, 2018Date of Patent: February 4, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dae Seong Lee, Min Su Kim
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Patent number: 10523188Abstract: A semiconductor device includes: first through fourth active regions spaced apart from one another; a first gate line disposed to overlap with the first and second active regions, but not with the third and fourth active regions, and to extend in a first direction; a second gate line disposed to overlap with the third and fourth active regions, but not with the first and second active regions, and to extend in the first direction while being spaced apart from the first gate line; and a dummy gate line disposed to overlap with the first through fourth active regions and a field region, to be spaced apart from the first and second gate lines in a second direction, and to extend in the first direction, wherein a signal input to the first or second active region is transmitted to the third or fourth active region.Type: GrantFiled: February 8, 2017Date of Patent: December 31, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Kyum Kim, Dae Seong Lee, Min Su Kim
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Publication number: 20190393205Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.Type: ApplicationFiled: January 17, 2019Publication date: December 26, 2019Inventors: Dae-Seong LEE, Ah-Reum KIM, Min-Su KIM, Jong-Kyu RYU
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Publication number: 20190379361Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.Type: ApplicationFiled: July 29, 2019Publication date: December 12, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul HWANG, Min-Su Kim, Dae-Seong Lee
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Publication number: 20190325107Abstract: An integrated circuit including standard cells, a method and a computing system for designing and fabricating the same are provided. A computer-implemented method involves placing, based on a standard cell library, standard cells of an integrated circuit to be fabricated, and routing the placed standard cells. A position of a first wiring of a placed cell among the placed standard cells may be adjusted based on a position of a second wiring used for the routing. The first wiring is provided from at least one standard cell, formed in a same layer as that of the second wiring, and spaced from the second wiring in a first direction. An integrated circuit layout having the adjusted position of the first wiring, is produced.Type: ApplicationFiled: April 18, 2019Publication date: October 24, 2019Inventors: KYUNG-BONG KIM, Min-su Kim, Dae-seong Lee
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Publication number: 20190267974Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Inventors: MIN SU KIM, Dae Seong Lee
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Patent number: 10396761Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.Type: GrantFiled: August 4, 2017Date of Patent: August 27, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Hwang, Min-Su Kim, Dae-Seong Lee
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Patent number: 10353000Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.Type: GrantFiled: April 5, 2017Date of Patent: July 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-Seok Yoon, Min-Su Kim, Chung-Hee Kim, Dae-Seong Lee, Hyun Lee, Matthew Berzins, James Lim
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Publication number: 20190214377Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.Type: ApplicationFiled: August 20, 2018Publication date: July 11, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Kyu RYU, Min-Su KIM, Yong-Geol KIM, Dae-Seong LEE
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Patent number: 10291212Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.Type: GrantFiled: May 2, 2018Date of Patent: May 14, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min Su Kim, Dae Seong Lee
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Publication number: 20190109586Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.Type: ApplicationFiled: May 16, 2018Publication date: April 11, 2019Inventors: HYUN LEE, DAE SEONG LEE, MINSU KIM, AHREUM KIM, CHUNGHEE KIM
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Publication number: 20190089338Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.Type: ApplicationFiled: May 2, 2018Publication date: March 21, 2019Inventors: Min Su Kim, Dae Seong Lee
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Publication number: 20190074296Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.Type: ApplicationFiled: April 26, 2018Publication date: March 7, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-kyu RYU, Min-su Kim, Dae-seong Lee
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Patent number: 10184984Abstract: An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.Type: GrantFiled: April 28, 2016Date of Patent: January 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Chul Hwang, Dae-Seong Lee, Min-Su Kim
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Publication number: 20180350815Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.Type: ApplicationFiled: August 9, 2018Publication date: December 6, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Dae Seong LEE, Min Su KIM
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Patent number: 10062697Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.Type: GrantFiled: February 9, 2017Date of Patent: August 28, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dae Seong Lee, Min Su Kim
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Publication number: 20180145661Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.Type: ApplicationFiled: August 4, 2017Publication date: May 24, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul HWANG, Min-Su Kim, Dae-Seong Lee