Patents by Inventor Dae-Seong LEE
Dae-Seong LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180131084Abstract: Disclosed is a printed circuit board (PCB) structure, in which an electromagnetic signal transmitting antenna and/or an electromagnetic signal receiving antenna, and an electromagnetic signal transferring tunnel (EM-tunnel) are embedded, the PCB structure including a PCB, an EM-tunnel that includes a dielectric core and a metal clad that surrounds the dielectric core and that is embedded in the PCB to be parallel to the PCB, and at least one transmitting antenna and/or at least one receiving antenna that are embedded in the PCB, wherein the transmitting antenna and/or the receiving antenna are arranged at an input port and an output port of the EM-tunnel embedded in the PCB to transmit and receive electromagnetic signals to and from the interior of the EM-tunnel.Type: ApplicationFiled: December 8, 2016Publication date: May 10, 2018Inventors: Hyo-Hoon PARK, Hyeon Min BAE, Ha Il SONG, Dae-Seong LEE, Harin LEE
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Patent number: 9966936Abstract: A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.Type: GrantFiled: June 3, 2016Date of Patent: May 8, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Kyum Kim, Dae-Seong Lee, Min-Su Kim
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Publication number: 20170292993Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.Type: ApplicationFiled: April 5, 2017Publication date: October 12, 2017Inventors: DOO-SEOK YOON, MIN-SU KIM, CHUNG-HEE KIM, DAE-SEONG LEE, HYUN LEE, MATTHEW BERZINS, JAMES LIM
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Patent number: 9780082Abstract: A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.Type: GrantFiled: February 24, 2016Date of Patent: October 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Seong Lee, Dae-Young Moon, Min-Su Kim
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Publication number: 20170244394Abstract: A semiconductor device includes: first through fourth active regions spaced apart from one another; a first gate line disposed to overlap with the first and second active regions, but not with the third and fourth active regions, and to extend in a first direction; a second gate line disposed to overlap with the third and fourth active regions, but not with the first and second active regions, and to extend in the first direction while being spaced apart from the first gate line; and a dummy gate line disposed to overlap with the first through fourth active regions and a field region, to be spaced apart from the first and second gate lines in a second direction, and to extend in the first direction, wherein a signal input to the first or second active region is transmitted to the third or fourth active region.Type: ApplicationFiled: February 8, 2017Publication date: August 24, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Kyum KIM, Dae Seong LEE, Min Su KIM
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Publication number: 20170236823Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.Type: ApplicationFiled: February 9, 2017Publication date: August 17, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Dae Seong LEE, Min Su KIM
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Publication number: 20170077910Abstract: A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.Type: ApplicationFiled: June 3, 2016Publication date: March 16, 2017Inventors: JI-KYUM KIM, DAE-SEONG LEE, MIN-SU KIM
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Publication number: 20170003343Abstract: An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.Type: ApplicationFiled: April 28, 2016Publication date: January 5, 2017Inventors: HYUN-CHUL HWANG, DAE-SEONG LEE, MIN-SU KIM
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Patent number: 9537470Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: GrantFiled: August 12, 2015Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee Kim, Min-Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae-Seong Lee, Gun-Ok Jung, Uk-Rae Cho
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Publication number: 20160268243Abstract: A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.Type: ApplicationFiled: February 24, 2016Publication date: September 15, 2016Inventors: DAE-SEONG LEE, DAE-YOUNG MOON, MIN-SU KIM
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Publication number: 20150349756Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee KIM, Min-Su KIM, Ji-Kyum KIM, Emil KAGRAMANYAN, Dae-Seong LEE, Gun-Ok JUNG, Uk-Rae CHO
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Patent number: 9130550Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: GrantFiled: June 4, 2014Date of Patent: September 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee Kim, Min-Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae-Seong Lee, Gun-Ok Jung, Uk-Rae Cho
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Publication number: 20140368246Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.Type: ApplicationFiled: June 4, 2014Publication date: December 18, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chung-Hee KIM, Min-Su KIM, Ji-Kyum KIM, Emil KAGRAMANYAN, Dae-Seong LEE, Gun-Ok JUNG, Uk-Rae CHO