Abstract: A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

Abstract: A number of read cycles applied to a selected memory location of a memory device, such as a variable-resistance memory device, is monitored. Write data to be written to the selected memory location is received. Selective pre-write verifying and writing of the received write data to the selected memory location occurs based on the monitored number of read cycles.

Abstract: A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained.

Abstract: Double gate transistors having at least two polysilicon patterns on a thin body used as an active region and methods of forming the same are provided. Embodiments of the transistors and methods provided are capable of enhancing current drivability of a semiconductor memory device using polysilicon patterns having different impurity concentrations from each other. In some embodiments an active region is protruded from a semiconductor substrate, an impurity diffusion region is formed in the active region, and a gate insulating pattern and a gate pattern are sequentially stacked on the active region. In these embodiments, the gate pattern may include polysilicon patterns having different impurity concentrations from each other.

Abstract: A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may surround sidewalls of the semiconductor region. An interlayer insulating layer may be on the semiconductor substrate, on the semiconductor region, and on the insulating isolation structure, and the interlayer insulating layer may have first and second spaced apart element holes exposing respective first and second portions of the semiconductor region. A first semiconductor pattern may be in the first element hole on the first exposed portion of the semiconductor region, and a second semiconductor pattern may be in the second element;hole on the second exposed portion of the semiconductor region.

Abstract: A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

Abstract: The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.

Abstract: A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

Abstract: A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract: A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract: In a semiconductor device having a recessed gate electrode and a method of fabricating the same, a channel trench is formed in a semiconductor substrate by etching the semiconductor substrate. A first semiconductor layer is formed on the semiconductor substrate that fills the channel trench. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer having a lower impurity concentration than the first semiconductor layer.

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate of the field region to define the active region, and has a protrusion higher than a surface of the semiconductor substrate. A gate pattern is formed on and across the semiconductor substrate of the active region, and has a top surface disposed on substantially the same plane as a top surface of the trench isolation layer. A gate line is formed, which is self-aligned with the gate pattern to cover the gate pattern and extends over the trench isolation layer. A reduction in an effective channel length of the device due to excess trapped electrons is prevented.

Abstract: Double gate transistors having at least two polysilicon patterns on a thin body used as an active region and methods of forming the same are provided. Embodiments of the transistors and methods provided are capable of enhancing current drivability of a semiconductor memory device using polysilicon patterns having different impurity concentrations from each other. In some embodiments an active region is protruded from a semiconductor substrate, an impurity diffusion region is formed in the active region, and a gate insulating pattern and a gate pattern are sequentially stacked on the active region. In these embodiments, the gate pattern may include polysilicon patterns having different impurity concentrations from each other.

Abstract: A method of forming bit line contact holes simultaneously in the cell array region and the peripheral circuit region through a single-step photolithographic process using an etching stop phenomenon. Bit line contact holes are formed to expose a contact pad in the cell array region, to expose impurity diffusion region and to expose a gate electrode of a transistor in the peripheral region. Bit line contact holes are formed by a two-step etching process. The first etching step etches selectively insulating layers against a capping nitride of a transistor in the peripheral region, using a predefined photoresist pattern, thereby forming a first bit line contact hole to the contact pad in the cell array region, a bit line contact hole to the impurity region in the peripheral and an opening to the capping layer in the peripheral region.

Abstract: A first conductive impurity ion is implanted into a semiconductor substrate to form a well area on which a gate electrode is formed. A first non-conductive impurity is implanted into the well area on both sides of the gate electrode to control a substrate defect therein and to form a first precipitate area to a first depth. A second conductive impurity ion is implanted into the well area on both sides of the gate electrode, so that a source/drain area is formed to a second depth being relatively shallower than the first depth. A second non-conductive impurity is implanted into the source/drain area so as to control a substrate defect therein and to form a second precipitate area. As a result, substrate defects such as dislocation, extended defect, and stacking fault are isolated from a P-N junction area, thereby forming a stable P-N junction.

Abstract: A method for forming a contact is provides that can minimize junction leakage. In this method, A contact hole is opened in an insulating layer to expose an impurity diffusion layer in a semiconductor substrate. A silicide layer is then selectively formed on the bottom of the contact hole, i.e., over the impurity diffusion layer. Impurity ions are then implanted into the impurity diffusion layer through the silicide layer so as to reduce contact resistance. The remainder of the contact hole is then filled with metal. Because of the presence of the silicide layer, ion implanting damages is confined to within the suicide layer, and there is no damage to the underlying impurity diffusion layer. As a result, silicon substrate defects can be minimized and a reliable junction without junction leakage can be obtained.