Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A reception interface circuit includes a reception buffer, a voltage generation circuit and a reception limiting circuit. The reception buffer receives an input signal through an input-output node to generate a buffer signal. The voltage generation circuit generates at least one control voltage based on a reflection characteristic at the input-output node. The reception limiting circuit is connected to the input-output node and limits at least one of a maximum voltage level and a minimum voltage level of the input signal based on the at least one control voltage. Power consumption may be reduced by limiting at least one of the maximum voltage level and the minimum voltage level of the input signal based on the reception characteristic at the input-output node using the reception limiting circuit, and an increased eye margin may be provided in comparison with a conventional termination circuit having the same power consumption.

Abstract: An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

Abstract: An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line.

Abstract: Disclosed are various embodiments for a clock and data recovery (CDR) system. The CDR system comprises a transition detection stage and a clock recovery stage. The transition detection stage is responsible for receiving the data signal and detecting whether a transition exists in the data signal by oversampling the data signal. The clock recovery stage generates a recovery clock based on whether there is a transition in the data signal.

Abstract: A system and method is disclosed for providing a robust ultra low power serial interface with a digital clock and data recovery circuit for power management systems. In one advantageous embodiment a digital clock and data recovery circuit of the invention comprises a quadruple phase clock generator circuit that generates four shifted clock signals, a decision logic circuit, a state detector circuit, and an edge detector circuit. The detected edges of data signals are used to latch the state of the four shifted clock signals. The state detector circuit selects a stable clock signal among the four shifted clock signals for use as a recovered clock signal and synchronizes the recovered clock signal at a center of the data signal. The selected recovered clock signal remains available until another data signal transition is detected.

Abstract: The present invention provides a versatile system for management of clocking for a serial interface. Serial input data, comprising a plurality of fields, and preceded by a specific input pattern, is provided to a receiver element. Within one of the fields in the serial input data, some information concerning the size the current serial data payload is included. Responsive to receiving the specific input pattern, the system of the present invention asserts a clock enable signal to activate clocking. A countdown corresponding to the size the current serial data payload is initiated. Once that countdown has reached zero, the clocking for the interface is disabled.

Abstract: A method for operating a power controller in a wireless communication device is provided that includes generating a power controller output signal using an open loop polar modulation scheme. The power controller output signal is operable to control the power delivered to a high-band power amplifier and a low-band power amplifier. A band state is determined for the wireless communication device. The power controller output signal is provided to the high-band power amplifier when the band state is a high-band state and to the low-band power amplifier when the band state is a low-band state.

Abstract: A system and method is disclosed that provides a digital self-adjusting power supply for semiconductor digital circuits. The power supply provides a substantially constant minimum supply voltage with regard to process corner, junction temperature, external voltage source, load variation, and operating frequency. The system comprises a slack time detector, a voltage adjuster, and a digital pulse width modulation (PWM) modulator. The system supplies a minimum required voltage without the used of a band gap or reference voltage. A finite state machine is also used to minimize oscillations introduced by start-up, load transients, frequency changes, and the like, thereby eliminating the need for a proportional integrator differentiator (PID) circuit.

Abstract: On-chip AC noise suppression is provided for a target circuit within an integrated circuit chip. A power supply line filter is provided in the power supply line that feeds the target circuit. The filter includes a polysilicon resistor formed over a charged substrate well, with a dielectric material interposed between the well and the resistor. This decreases capacitive coupling between the substrate and the resistor, thereby suppressing AC noise that is injected via the substrate. For an on-chip bandgap reference circuit, AC noise suppression can be achieved by providing matched AC impedances in the PTAT and inverse PTAT branches of the circuit. This technique exploits the common-mode rejection capability of the error amplifier within the bandgap reference circuit. Also, the inputs of the error amplifier can be capacitively coupled together to exploit the amplifier's common-mode rejection capability for the suppression of AC noise that is injected at the amplifier inputs.

Abstract: A semiconductor device is provided including a printed circuit board and first, second and third rows of power and/or signal pads on the printed circuit board. A plurality of input and output buffers are also provided. Ones of the plurality of input and output buffers are provided between the first and second rows and others of the plurality of input and output buffers are provided between the second and third rows. Related methods of fabricating semiconductor devices are also provided.

Abstract: A method includes generating multiple delayed versions of a first signal using at least one first delay line, selecting at least one version of the first signal, and generating a second signal based on the at least one selected version of the first signal. The method also includes generating multiple delayed versions of the second signal using at least one second delay line, and selecting at least one version of the second signal. In addition, the method includes modifying selection of the at least one version of the first signal and the at least one version of the second signal to achieve a desired output signal. This method could be used in various circuits, such as duty cycle correction circuits, frequency multiplier circuits, and digital multiphase oscillator circuits.

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.