Abstract: A backlight unit and a display device having the same are discussed. According to an embodiment, the backlight unit includes a light source configured to generate light; and a light guide plate configured to distribute the light received from the light source, the light guide plate including: at least one body, each of the at least one body divided into a plurality of blocks, and a plurality of reflective patterns formed on a bottom surface of the body, wherein the plurality of reflective patterns are selectively provided at some of the plurality of blocks.

Abstract: A method for executing an operation on a portable terminal in a locked state includes displaying a lockscreen on the portable terminal including state information of the portable terminal; receiving an input on the lockscreen; determining whether the input corresponds to an operation of an application with respect to the displayed state information; and executing the operation according to the determination. A portable terminal includes an interface unit to output a lockscreen when the portable terminal is in a locked state and to display state information on the lockscreen; an input unit to receive an input; a verification unit to determine whether the input corresponds to an operation of an application with respect to the determined state information; and an execution unit to execute the predetermine operation.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract: A method of fabricating a semiconductor includes providing a substrate having a first region and a second region defined therein, forming a first gate and a first source and drain region in the first region and forming a second gate and a second source and drain region in the second region, forming an epitaxial layer in the second source and drain region, forming a first metal silicide layer in the first source and drain region, forming an interlayer dielectric layer on the first region and the second region, forming a plurality of contact holes exposing the first metal silicide layer and the epitaxial layer while penetrating the interlayer dielectric layer, forming a second metal silicide layer in the exposed epitaxial layer, and forming a plurality of contacts contacting the first and second metal silicide layers by filling the plurality of contact holes.

Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.

Abstract: Disclosed are a vacuum channel transistor including a planar cathode layer formed of a material having a low work function or a planar cathode layer including a heat resistant layer formed of a material having a low work function, and a manufacturing method of the same. In the vacuum channel transistor, electrons can be emitted even when a low voltage is applied to a gate layer, a voltage of an anode layer has a small influence on electron emission of a cathode layer, and instability of emission current is obviated. Accordingly, high efficiency and a long lifespan can be achieved, and thus operational stability is secured.

Abstract: A flash memory device and a method of testing the flash memory device are provided. The flash memory device may include a memory cell array including a plurality of bit lines, a control unit configured to output estimated data and an input/output buffer unit including a plurality of page buffers. Each of the plurality of page buffers corresponds to one of the plurality of bit lines in the memory cell array and is configured to read test data programmed in at least a first page of a memory cell array, compare the read-out test data with the estimated data to determine whether the corresponding bit line is in a pass or failure state and output a test result signal. A voltage of the test result signal is maintained when test data of a second page of the memory cell array is read if the corresponding bit line in the first page is in a failure state.

Abstract: Provided is a method for producing a cloned dog by enucleating an oocyte of a dog to produce an enucleated oocyte, transferring a somatic cell of the dog into the enucleated oocyte, carrying out electrofusion under optimized conditions to produce a nuclear transfer embryo, and transferring the nuclear transfer embryo into its surrogate mother.

Abstract: A user equipment to display an augmented reality (AR) window includes a display unit to display an image and AR windows corresponding to objects included in the image, and a control unit to determine an arrangement pattern of the AR windows by adjusting at least one of a size, a display location, a display pattern, and a color of the AR windows and to control the display unit to display the AR windows in the determined arrangement pattern, together with the objects. A method includes detecting the object in the image, generating the AR window corresponding to the object, determining an arrangement pattern of the AR window based on an adjustment of an attribute, and displaying the AR window in the determined arrangement pattern along with the object.

Abstract: Provided are a transistor and a method of manufacturing the transistor, and more particularly, a vacuum channel transistor emitting thermal cathode electrons and a method of manufacturing the vacuum channel transistor. The vacuum channel transistor includes: a motherboard; a micro heater member having a thin-film structure formed on the motherboard; a cathode member having a thin-film structure spaced apart from a center part of the micro heater member by a first interval and formed on the micro heater member; a gate member formed on both outer walls of upper parts of the cathode member; and an anode member spaced apart from the cathode member by a second interval through spacers disposed on the gate member, wherein a vacuum electron passing area is interposed between the cathode member and the anode member by the second interval.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line, and the de-coupling transistor is formed in the well.

Abstract: In one embodiment, the non-volatile memory device includes a well of a first conductivity type formed in a substrate, and a first plurality of memory cell transistors connected in series to a bit line formed in the well. A buffer is formed in the substrate outside the well and is connected to the bit line. At least one de-coupling transistor is configured to de-couple the buffer from the bit line; and the de-coupling transistor is formed in the well.

Abstract: A first terminal shares a digital marker edited in a digital marker editing mode and an object corresponding to the edited digital marker with a second terminal using a wireless communication technology. If a digital marker is displayed on an image display unit of the first terminal, the second terminal photographs the digital marker using a camera, and synthesizes an object corresponding to the photographed digital marker with a real-time video image obtained through the camera to display a merged image as augmented reality. Then, the second terminal receives input information for changing the digital marker from a user, and transmits the received input information to the first terminal. The first terminal changes a digital marker using the input information received from the second terminal. The second terminal photographs the changed digital marker, and displays an object corresponding to the changed digital marker.

Abstract: An overvoltage protection control circuit includes a voltage conversion circuit, a voltage comparison circuit, and a switching circuit. The voltage conversion circuit generates a first voltage and a second voltage based on a power supply voltage. The voltage comparison circuit generates a control signal based on a comparison between the first voltage and the second voltage. The switching circuit determines whether to apply the power supply voltage to a chip in response to the control signal. The overvoltage protection control circuit is formed inside the chip.

Abstract: A mobile communication terminal having an image conversion function arranges and displays area-specific images in a three-dimensional (3D) space on the basis of distance information of the area-specific images of a two-dimensional (2D) image.

Abstract: A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly coveri

Abstract: A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers.

Abstract: Provided are a MIT device self-heating preventive-circuit that can solve a self-heating problem of a MIT device and a method of manufacturing a MIT device self-heating preventive-circuit integrated device. The MIT device self-heating preventive-circuit includes a MIT device that generates an abrupt MIT at a temperature equal to or greater than a critical temperature and is connected to a current driving device to control the flow of current in the current driving device, a transistor that is connected to the MIT device to control the self-heating of the MIT device after generating the MIT in the MIT device, and a resistor connected to the MIT device and the transistor.

Abstract: A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide layer from the silicon bearing layer and the metal layer using a silicidation process. Also, a method of forming metal wiring in a semiconductor device using the foregoing method of forming an ohmic contact layer.

Abstract: A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures.