Abstract: Provided is a high-speed electron beam lithography system including a transfer chamber; a plurality of electron beam lithography chambers, each of which is connected to the transfer chamber and includes a multicolumn portion; and input and output loadlock chambers, each of which is connected to the transfer chamber. Herein, the plurality of electron beam lithography chambers and the input and output loadlock chambers are connected to the transfer chamber, forming a cluster. Also, a plurality of wafers are respectively loaded into the plurality of electron beam lithography chambers so as to drive the electron beam lithography chambers at the same time.

Abstract: The present invention relates to a deflector of a micro-column electron beam apparatus and method for fabricating the same, which forms a seed metal layer and a mask layer on both sides of a substrate, and exposes some of the seed metal layer on which deflecting plates, wirings and pads are to be formed by lithography process using a predetermined mask. The wirings and pads are formed by plating metal on the exposed portion, and some of the metal layer is also exposed on which the deflecting plates are to be formed using a predetermined mask, and then the metal is plated with desired thickness, thereby the deflecting plates are completed. Therefore, by forming plurality of deflecting plates on both sides of the substrate at the same time through plating process, alignment between the deflecting plates formed on both sides of the substrate can be exactly made, and by fabricating a deflector integrated with the substrate and deflecting plates in a batch process, productivity and reproducibility is improved.

Abstract: An apparatus for measuring a gap between a mask and a substrate and a method thereof are provided. The apparatus includes a laser displacement sensor, which is placed on a mask and a substrate spaced apart from each other by a predetermined gap, emits laser beams while moving onto the mask and the substrate in a horizontal direction and measures a gap between the mask and the substrate using a variation in distance values measured based on light-receiving positions of the laser beams that are reflected from the mask and the substrate and return to their original positions, respectively.

Abstract: The present invention relates to a deflector of a micro-column electron beam apparatus and method for fabricating the same, which forms a seed metal layer and a mask layer on both sides of a substrate, and exposes some of the seed metal layer on which deflecting plates, wirings and pads are to be formed by lithography process using a predetermined mask. The wirings and pads are formed by plating metal on the exposed portion, and some of the metal layer is also exposed on which the deflecting plates are to be formed using a predetermined mask, and then the metal is plated with desired thickness, thereby the deflecting plates are completed. Therefore, by forming plurality of deflecting plates on both sides of the substrate at the same time through plating process, alignment between the deflecting plates formed on both sides of the substrate can be exactly made, and by fabricating a deflector integrated with the substrate and deflecting plates in a batch process, productivity and reproducibility is improved.

Abstract: The present invention relates to a deflector of a micro-column electron beam apparatus and method for fabricating the same, which forms a seed metal layer and a mask layer on both sides of a substrate, and exposes some of the seed metal layer on which deflecting plates, wirings and pads are to be formed by lithography process using a predetermined mask. The wirings and pads are formed by plating metal on the exposed portion, and some of the metal layer is also exposed on which the deflecting plates are to be formed using a predetermined mask, and then the metal is plated with desired thickness, thereby the deflecting plates are completed. Therefore, by forming plurality of deflecting plates on both sides of the substrate at the same time through plating process, alignment between the deflecting plates formed on both sides of the substrate can be exactly made, and by fabricating a deflector integrated with the substrate and deflecting plates in a batch process, productivity and reproducibility is improved.

Abstract: A method of fabricating a resist pattern for a gamma gate of high electron mobility transistors of gallium arsenide (GaAs) elements for high-speed data communication with low noise is disclosed. The method of fabricating the gamma gate according to the present invention includes the steps of forming a first resist pattern by coating a first resist on a GaAs substrate, and exposing, developing and baking the coated first resist, sequentially; and forming a second resist pattern by coating a second resist on the GaAs substrate and the first resist pattern. and exposing, developing and baking the coated second resist, sequentially. A portion of the GaAs substrate covered by the first and the second resist patterns defines a region that a footprint of the gamma gate is formed, and a portion of the GaAs substrate which is covered by the first resist pattern, but not covered by the second resist pattern defines a region that a head of the gamma gate is formed.

Abstract: The present invention provides an optical system for crystallization tool for producing an crystallized silicon thin film by using an excimer laser as a light source to crystallize an amorphous silicon thin film through a fine stripped pattern, including 1st to 10th lenses sequentially arranged along an optical axis from said excimer laser, wherein the 1st lens having both side made convex; the 2nd lens having one side made convex toward the light source and the other side concave; the 3rd lens having one side made convex toward the light source and the other side concave; the 4th lens having both side concave; the 5th lens having both side made convex; the 6th lens having one side concave toward the light source and the other side made convex; the 7th lens having one side made convex toward the light source and the other side concave; the 8th lens having both side made convex; the 9th lens having one side made convex toward the light source and the other side concave; and the 10th lens having both side made

Abstract: The RF active balun circuit for improving a small-signal linearity in a power amplifying circuit of a CDMA system is provided under the construction of a signal amplifier driven by exterior individual direct current gate power VGG1, VGG2, for receiving a communication input signal AC-In and performing a cascode amplification at a normal operation point where a feedback third-order distortion signal becomes large; a distortion signal generator driven by exterior direct current gate power VGG3 different from the above power, for generating the communication input signal AC-In as the third-order distortion signal by nonlinearity of an active element to cancel the third-order distortion signal amplified in the signal amplifier; and an insulator provided for an insulation from a exterior driving power VGG3 applied to the distortion signal generator, thereby maintaining the small size, lower power and high efficient terminal characteristics by using a gain based on gate voltage of FET and the nonlinearity character

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing step

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing step

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing step

Abstract: A method for fabricating an inductor device includes the steps of forming a plurality of trenches in a substrate by selectively etching the substrate, implanting dopants into sidewalls and bottom portion of each trench, forming an oxide layer by oxidizing the trenches and the substrate and simultaneously forming a doped layer in the surroundings of the trenches by diffusing the dopants into the substrate, and forming a dielectric layer on a resultant structure to fill the entrance of the trenches, thereby forming air-gap layers inside the trenches, thereby reducing a parasitic capacitance and a magnetic coupling.

Abstract: The present invention provides an optical system for crystallization tool for producing an crystallized silicon thin film by using an excimer laser as a light source to crystallize an amorphous silicon thin film through a fine stripped pattern, including 1st to 10th lenses sequentially arranged along an optical axis from said excimer laser, wherein the 1st lens having both side made convex; the 2nd lens having one side made convex toward the light source and the other side concave; the 3rd lens having one side made convex toward the light source and the other side concave; the 4th lens having both side concave; the 5th lens having both side made convex; the 6th lens having one side concave toward the light source and the other side made convex; the 7th lens having one side made convex toward the light source and the other side concave; the 8th lens having both side made convex; the 9th lens having one side made convex toward the light source and the other side concave; and the 10th lens having both side made

Abstract: Provided is a method of fabricating a vacuum micro-structure, which is used for an element operating in a vacuum, the method comprising the steps of: (1) entirely etching an epitaxial layer of a silicon substrate having an SOI structure including an upper silicon epitaxial layer, an interlevel insulating layer and a lower silicon bulk layer to form two electrode structures and a floating vibratory structure, and encapsulating them with a vacuum sealing substrate in a vacuum; and (2) etching the silicon substrate having the SOI stricture from the back side to the interlevel insulating layer to open the electrode structures, and forming a metal electrode.

Abstract: Integrated circuit memory devices include overlapping bit lines and power supply lines. The integrated circuit memory devices include a memory cell array in an integrated circuit substrate and a plurality of spaced apart bit lines on the memory cell array, extending in a first direction. A plurality of spaced apart power lines are also included on the memory cell array, extending in the first direction, and on at least one of the plurality of bit lines. The overlapping bit lines and power supply lines are insulated from one another, for example by providing these lines in first and second patterned conductive layers. Accordingly, higher density integrated circuit devices may be provided while allowing high speed operation and effective power supply voltage distribution.

Abstract: The present invention relates to an agitator for suspension polymerization having a more improved structure in effect in contrast to the earlier agitator. The present invention also relates to an improved suspension polymerization method of vinyl chloride using a polymerization reactor equipped with that agitator, by which vinyl chloride resin having excellent quality can be prepared with a diminution of the number of fish eyes which cause many problems such as deterioration of the processed article, low productivity, etc.

Abstract: A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.