Abstract: A stocker for holding a plurality of reticle pods is provided. Each of the reticle pods is configured to accommodate a reticle assembly. The reticle assembly includes a reticle and a pellicle covering the reticle. The stocker includes a main frame and an electrostatic generator. The main frame has an inner space and at least one pod support disposed in the inner space. The pod support divides the inner space into a plurality of chambers configured to respectively accommodate the plurality of reticle pods. The electrostatic generator is coupled to the reticle assembly and configured to generate static electricity to the reticle assembly. The static electricity alternates between positive electricity and negative electricity.

Abstract: A reticle stage for holding a reticle assembly is provided. The reticle assembly has a reticle and a pellicle covering the reticle. The reticle stage includes a reticle stage base, a reticle holder disposed on the reticle stage base and for holding the reticle assembly over the reticle stage base, and an electrostatic generator coupled to the reticle assembly. The electrostatic generator is configured to generate static electricity to the reticle assembly. The static electricity alternates between positive electricity and negative electricity.

Abstract: A stocker for holding a plurality of reticle pods is provided. Each of the reticle pods is configured to accommodate a reticle assembly. The reticle assembly includes a reticle and a pellicle covering the reticle. The stocker includes a main frame and an electrostatic generator. The main frame has an inner space and at least one pod support disposed in the inner space. The pod support divides the inner space into a plurality of chambers configured to respectively accommodate the plurality of reticle pods. The electrostatic generator is coupled to the reticle assembly and configured to generate static electricity to the reticle assembly. The static electricity alternates between positive electricity and negative electricity.

Abstract: Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.

Abstract: Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.

Abstract: A method of detecting reticle error may include using an optical source of an exposure unit to cause light to be incident on a reticle installed in the exposure unit, and detecting the reticle error using only 0th diffraction light from among diffraction lights transmitted through the reticle. A method of detecting reticle error may include: installing a reticle, including a mask substrate and mask patterns having a critical dimension formed on the mask substrate, in an exposure unit to cause light to be incident on the reticle; exposing a photoresist film disposed on a wafer in the exposure unit using only 0th diffraction light from among diffraction lights transmitted through the reticle; developing the exposed photoresist film; and analyzing a thickness change, an image, or the thickness change and image of the developed photoresist film, in order to detect the reticle error at a wafer level.

Abstract: Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern.

Abstract: Provided is a photomask used in fabrication of a semiconductor device. The photomask includes first and second regions to be transferred onto a semiconductor substrate having a step difference. The first and second regions have mask patterns. The mask patterns of the first region have a different shape from the mask patterns of the second region. The mask patterns of the second region have concave and convex portions disposed in opposite lateral portions thereof.

Abstract: Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.

Abstract: Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern.

Abstract: Provided is a photomask used in fabrication of a semiconductor device. The photomask includes first and second regions to be transferred onto a semiconductor substrate having a step difference. The first and second regions have mask patterns. The mask patterns of the first region have a different shape from the mask patterns of the second region. The mask patterns of the second region have concave and convex portions disposed in opposite lateral portions thereof.

Abstract: Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.

Abstract: A method of detecting reticle error may include using an optical source of an exposure unit to cause light to be incident on a reticle installed in the exposure unit, and detecting the reticle error using only 0th diffraction light from among diffraction lights transmitted through the reticle. A method of detecting reticle error may include: installing a reticle, including a mask substrate and mask patterns having a critical dimension formed on the mask substrate, in an exposure unit to cause light to be incident on the reticle; exposing a photoresist film disposed on a wafer in the exposure unit using only 0th diffraction light from among diffraction lights transmitted through the reticle; developing the exposed photoresist film; and analyzing a thickness change, an image, or the thickness change and image of the developed photoresist film, in order to detect the reticle error at a wafer level.

Abstract: An overlay key formed in a scribe lane and used to align a circuit pattern may include a lower overlay mark formed on a metal silicide layer directly in contact with a silicon substrate. A method of forming an overlay key in a scribe lane may include providing a silicon substrate, forming a metal silicide layer to be in direct contact with the silicon substrate, and forming a lower overlay mark on the metal silicide layer.

Abstract: In a method of manufacturing a non-volatile semiconductor memory device that includes a first region having a first gate structure and a second region having a second gate structure, the first gate structure may include a tunnel oxide layer pattern, a first conductive layer pattern, a dielectric layer pattern and a second conductive layer pattern. A first photoresist pattern may be formed on the second conductive layer pattern to form a source line which may be formed in a region of the first area by implanting impurities. A second photoresist pattern may be formed on a hard mask layer in the second region of the substrate to form a hard mask pattern on a third conductive layer. The second gate structure having substantially vertical sidewalls may be formed in the second area by etching the third conductive layer using the hard mask pattern.

Abstract: Disclosed is a method for manufacturing a semiconductor device by employing a dual damascene process. After a first insulation film including a conductive pattern is formed on a substrate, at least one etch stop film and at least one insulation film are alternatively formed on the first insulation film. A via hole for a contact or a trench for a metal wiring is formed through the insulation film, and then the via hole or the trench is filled with a filling film including a water-soluble polymer. After a photoresist film is coated on the filling film, the photoresist film is patterned to form a photoresist pattern and to remove the filling film. The DOF and processing margin of the photolithography process for forming the photoresist pattern can be improved because the photoresist film can have greatly reduced thickness due to the filling film.

Abstract: A structure, which may be provided on an overlay region for an overlay mark, may include a first pattern that may project from a peripheral portion of the overlay region that may be defined on a scribe lane of a substrate. A second pattern may project from a central portion of the overlay region.

Abstract: Correcting light intensity for photolithography may include irradiating light having a first light intensity distribution through a photo mask having a mask pattern to a photosensitive layer on a wafer to form a first pattern corresponding to the mask pattern. A distribution of critical dimensions of the first pattern corresponding to the mask pattern may be determined, and a second light intensity distribution may be determined based on a relation between the first light intensity distribution and the distribution of critical dimensions of the first pattern. Then, light having the second light intensity distribution may be irradiated. Related systems are also discussed.

Abstract: A method for forming a minute pattern includes forming a mask layer on an object being patterned. The mask layer is patterned to form a first mask pattern having a first width larger than a predetermined width. The first mask pattern is thermally treated to form a second mask pattern having a second width smaller than the first width. A polymer layer is formed on the second mask pattern. The polymer layer reacts with the second mask pattern to form a hardened layer on a boundary surface between the polymer layer and the second mask pattern, thereby forming a third mask pattern having a third width substantially identical to the predetermined width. The limits of the present photolithography equipment are overcome. Also, a semiconductor device having a CD of below about 100 nm is manufactured.

Abstract: A photoresist composition may include formulas 1 and 2: ?where R is an acetal group or a ter-butyloxy carbonyl (t-BOC) group, n and m are integers, n/(m+n) is 0.01?0.8, and m/(m+n) is 1?[n/(m+n)], ?where r is an integer between 8-40. A method for forming photoresist patterns may include forming a photoresist layer on a semiconductor substrate and exposing and developing the photoresist layer using a mask pattern that includes first areas having a light transmissivity of about 100% and second areas having a light transmissivity of between about 10% and about 30%.