Abstract: A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+ doped portion of a first region and a second opening is formed in the gate structure layers over the N+ doped portion of a second region. A gate dielectric layer is then formed on an inner side of the first and second openings. The surface of the semiconductor substrate in the first and second openings is etched. A semiconductor material is formed in the first and second openings by selective epitaxial growth.

Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Abstract: A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element.

Abstract: A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element such as a magnetic tunnel junction formed on a spin orbit torque layer. The vertical transistor structure selectively provides an electrical current to the spin orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high electrical current needed to provide spin orbit torque switching while also consuming a small amount of wafer real estate. The vertical transistor structure can include a semiconductor pillar structure surrounded by a gate dielectric layer and a gate structure such that the gate dielectric layer separates the gate structure from the semiconductor pillar.

Abstract: A magnetic memory structure that includes a two-terminal resistive memory element electrically connected with a selector structure. The selector structure includes a semiconductor pillar structure formed on a semiconductor substrate. The selector structure is surrounded by a gate dielectric layer, and the semiconductor pillar structure and gate dielectric layer are surrounded by an electrically conductive gate structure. The semiconductor pillar has first and second dimensions in a plane parallel with the surface of the semiconductor substrate that are unequal with one another. The semiconductor pillar structure can have a cross-section parallel with the semiconductor substrate surface that is in the shape of a: rectangle; oval elongated polygon, etc. The length of the longer dimension can be adjusted to provide a desired amount of current though the semiconductor pillar structure to drive the two-terminal resistive memory element.

Abstract: A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate electronical material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region over the substrate, and forming a first gate region over the first isolation region.

Abstract: A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

Abstract: A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.

Abstract: A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element such as a magnetic tunnel junction formed on a spin orbit torque layer. The vertical transistor structure selectively provides an electrical current to the spin orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high electrical current needed to provide spin orbit torque switching while also consuming a small amount of wafer real estate. The vertical transistor structure can include a semiconductor pillar structure surrounded by a gate dielectric layer and a gate structure such that the gate dielectric layer separates the gate structure from the semiconductor pillar.

Abstract: A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element.

Abstract: A method for manufacturing an inverter circuit includes providing a semiconductor substrate and forming at least one dielectric trench isolation structure in the semiconductor substrate to divide the semiconductor substrate into first and second regions. A P+ doped portion and an N+ doped portion is formed in each of the first and second regions. Gate structure layers are then deposited over the semiconductor substrate. A first opening is formed in the gate structure layers over the P+ doped portion of a first region and a second opening is formed in the gate structure layers over the N+ doped portion of a second region. A gate dielectric layer is then formed on an inner side of the first and second openings. The surface of the semiconductor substrate in the first and second openings is etched. A semiconductor material is formed in the first and second openings by selective epitaxial growth.

Abstract: In accordance with one embodiment, a method includes forming a cleavable donor substrate, the substrate including monocrystalline Si, forming a dielectric layer above the substrate in a film thickness direction, and cleaving the substrate into an upper portion having the dielectric layer and a lower portion. In one embodiment, the cleavable substrate is formed using a sacrificial buffer layer above the substrate in the film thickness direction, and forming a strained Si layer above the sacrificial buffer layer in the film thickness direction, followed by etching away the sacrificial buffer layer to cleave the substrate. In another embodiment, the cleavable substrate is formed by implanting ions into the substrate to a peak implant position located below an upper surface of the substrate, annealing the substrate and dielectric layer in an inert environment to form blisters at the peak implant position, and cleaving the substrate using the blisters.

Abstract: A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.

Abstract: A dynamic random access memory element that includes a vertical semiconductor transistor element formed on a substrate and electrically connected with a memory element such as a capacitive memory element. The memory element is located above the semiconductor substrate such that the vertical transistor is between the memory element and the substrate. The vertical semiconductor transistor is formed on a heavily doped region of the substrate that is separated from other portions of the substrate by a dielectric isolation layer. The heavily doped region of the semiconductor substrate provides electrical connection between the vertical transistor structure and a bit line. The dynamic random access memory element also includes a word line that includes an electrically conductive gate layer that is separated from the semiconductor pillar by a gate dielectric layer.

Abstract: A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region.

Abstract: Aspects of the present technology are directed toward Integrated Circuits (IC) including a plurality of trenches disposed in a substrate about a set of silicide regions. The trenches can extend down into the substrate below the set of silicide regions. The silicide regions can be formed by implanting metal ions into portions of a substrate exposed by a mask layer with narrow pitch openings. The trenches can be formed by selectively etching the substrate utilizing the set of silicide regions as a trench mask. An semiconductor material with various degree of crystallinity can be grown from the silicide regions, in openings that extend through subsequently formed layers down to the silicide regions.

Abstract: A transistor structure, according to one embodiment, includes: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel. The second side of the vertical channel is opposite the first side of the vertical channel along a plane perpendicular to a deposition direction. A magnetic device, according to another embodiment, includes: a plurality of transistor structures, each of the transistor structures comprising: an epitaxially grown vertical channel, a word line which surrounds a middle portion of the vertical channel, and a p-MTJ sensor coupled to a first end of the vertical channel.

Abstract: A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.

Abstract: A DRAM memory cell and memory cell array incorporating a metal silicide bit line buried within a doped portion of a semiconductor substrate and a vertical semiconductor structure electrically connected with a memory element such as a capacitive memory element. The buried metal silicide layer functions as a bit buried bit line which can provide a bit line voltage to the capacitive memory element via the vertical transistor structure. The buried metal silicide layer can be formed by allotaxy or mesotaxy. The vertical semiconductor structure can be formed by epitaxially growing a semiconductor material on an etched surface of the doped portion of the semiconductor substrate.

Abstract: A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region.