Abstract: Provided is a defect detection apparatus capable of scalably improving processing performance for image processing, even though a plurality of multi-core processors are used therein. The defect detection apparatus comprises: an imaging unit for taking images of a sample forming a pattern, a dividing part 4b for dividing image data taken by the imaging unit into a plurality of image data blocks, and a parallel processing unit 5 for parallelly performing pieces of a defect detection processing for the plurality of the image data blocks to detect a defect in the pattern. Herein, the parallel processing unit uses a plurality of multi-core processors having a plurality of cores. The defect inspection processing of the image data block is performed per the multi-core processor.

Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Abstract: A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Abstract: In a distributed control system in which a plurality of nodes are connected to a transmission line, each node controlling components connected to this node and transmitting a message to other nodes, a message sent by each node includes at least two message-sending condition-identifying portions, one of the condition-identifying portions including data indicating a message-receiving node or non-designation of a message-receiving node; and a comparison-selection circuit provided in each node includes registration parts for registering data of message-receiving conditions, at least two registration parts for comparing contents of the condition-identifying portion in the taken-in message with the data of message-receiving conditions registered in the registration parts, a received-message storing part for storing a message to be received in this node, a control part for determining whether or not the taken-in message is to be received in this node based on a result of comparison-processing performed in the compar

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: In a distributed control system in which a plurality of nodes are connected to a transmission line, each node controlling components connected to this node and transmitting a message to other nodes, a message sent by each node includes at least two message-sending condition-identifying portions, one of the condition-identifying portions including data indicating a message-receiving node or non-designation of a message-receiving node; and a comparison-selection circuit provided in each node includes registration parts for registering data of message-receiving conditions, at least two registration parts for comparing contents of the condition-identifying portion in the taken-in message with the data of message-receiving conditions registered in the registration parts, a received-message storing part for storing a message to be received in this node, a control part for determining whether or not the taken-in message is to be received in this node based on a result of comparison-processing performed in the compar

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Abstract: In a distributed control system in which a plurality of nodes are connected to a transmission line, each node controlling components connected to this node and transmitting a message to other nodes, a message sent by each node includes at least two message-sending condition-identifying portions, one of the condition-identifying portions including data indicating a message-receiving node or non-designation of a message-receiving node; and a comparison-selection circuit provided in each node includes registration parts for registering data of message-receiving conditions, at least two registration parts for comparing contents of the condition-identifying portion in the taken-in message with the data of message-receiving conditions registered in the registration parts, a received-message storing part for storing a message to be received in this node, a control part for determining whether or not the taken-in message is to be received in this node based on a result of comparison-processing performed in the compar

Abstract: In a distributed control system in which a plurality of nodes are connected to a transmission line, each node controlling components connected to this node and transmitting a message to other nodes, a message sent by each node includes at least two message-sending condition-identifying portions, one of the condition-identifying portions including data indicating a message-receiving node or non-designation of a message-receiving node; and a comparison-selection circuit provided in each node includes registration parts for registering data of message-receiving conditions, at least two registration parts for comparing contents of the condition-identifying portion in the taken-in message with the data of message-receiving conditions registered in the registration parts, a received-message storing part for storing a message to be received in this node, a control part for determining whether or not the taken-in message is to be received in this node based on a result of comparison-processing performed in the compar

Abstract: In a distributed control system with a plurality of nodes connected to a transmission line, each node controlling components and transmitting a message to other nodes, a message includes at least two message-sending condition-identifying portions, one of the portions including data indicating a message-receiving node or non-designation of a message-receiving node.

Abstract: In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: In a distributed control system in which a plurality of nodes are connected to a transmission line, each node controlling components connected to this node and transmitting a message to other nodes, a message sent by each node includes at least two message-sending condition-identifying portions, one of the condition-identifying portions including data indicating a message-receiving node or non-designation of a message-receiving node; and a comparison-selection circuit provided in each node includes registration parts for registering data of message-receiving conditions, at least two registration parts for comparing contents of the condition-identifying portion in the taken-in message with the data of message-receiving conditions registered in the registration parts, a received-message storing part for storing a message to be received in this node, a control part for determining whether or not the taken-in message is to be received in this node based on a result of comparison-processing performed in the compar