Abstract: In a distributed control system in which a plurality of nodes are connected to a transmission line, each node controlling components connected to this node and transmitting a message to other nodes, a message sent by each node includes at least two message-sending condition-identifying portions, one of the condition-identifying portions including data indicating a message-receiving node or non-designation of a message-receiving node; and a comparison-selection circuit provided in each node includes registration parts for registering data of message-receiving conditions, at least two registration parts for comparing contents of the condition-identifying portion in the taken-in message with the data of message-receiving conditions registered in the registration parts, a received-message storing part for storing a message to be received in this node, a control part for determining whether or not the taken-in message is to be received in this node based on a result of comparison-processing performed in the compar

Abstract: In a DMA controller having such a structure capable of readily changing a total channel number, a channel number depending unit for handling a signal related to the total channel number; an instance capable unit which can be repeatedly used plural times equal to the total channel number; and also a channel number not-depending unit are extracted from the respective functions of the DAM controller. Then, these extracted units are combined with each other so as to constitute a functional block of the DMA controller circuit. In such a case that a total device number is changed, since only the channel number depending unit may be merely corrected, a total number of correcting stages can be reduced. The reuse rate of the channel number not-depending unit may be increased.

Abstract: In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.