Patents by Inventor Daido Komyoji

Daido Komyoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11577490
    Abstract: A heat insulating material includes an aerogel that has macro-pores and meso-pores. A method for manufacturing a heat insulating material, including: a sol preparation step of adding a gelling agent into sodium silicate such that a molar ratio of the gelling agent relative to NaO2 is 0.1 to 0.75, and adjusting a sol into which macro-pores are introduced by leaving unreacted Na and non-cross-linked oxygen in a siloxane skeleton; an impregnating and gelling step of impregnating a nonwoven fabric fiber structure with the sol to form a composite of hydrogel-nonwoven fabric fiber; a hydrophobizating step of mixing the formed composite of hydrogel-nonwoven fabric fiber with a silylating agent to modify a surface thereof; and a drying step of removing a liquid contained in the surface modified composite of hydrogel-nonwoven fabric fiber by drying under a temperature and pressure lower than respective critical values.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 14, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kazuma Oikawa, Shigeaki Sakatani, Kazuhiro Nishikawa, Daido Komyoji
  • Publication number: 20200378058
    Abstract: A manufacturing method of a heat insulating sheet of the present disclosure includes a composite generating step of impregnating a nonwoven fiber with a basic sol prepared to generate a composite of a hydrogel-nonwoven fiber, the basic sol being prepared by adding carbonate ester to a water glass composition; and a drying step of drying a liquid contained in the composite at a temperature lower than a critical temperature of the liquid and a pressure lower than a critical pressure of the liquid to remove the liquid from the composite. A heat insulating sheet according to the present disclosure includes an aerogel and a nonwoven fiber, and has a compression rate at 0.30 MPa to 5.0 MPa of 40% or less. In an electronic device of the present disclosure, the heat insulating sheet is disposed between an electronic component and a housing. In a battery unit of the present disclosure, the heat insulating sheet is disposed between batteries.
    Type: Application
    Filed: May 18, 2020
    Publication date: December 3, 2020
    Inventors: KAZUMA OIKAWA, TOORU WADA, SHIGEKI SAKAGUCHI, TAKASHI KUBO, TAKASHI TSURUTA, SHIGEAKI SAKATANI, DAIDO KOMYOJI
  • Publication number: 20200309636
    Abstract: A state detection apparatus includes a state detection sensor that is attached to an architecture and that detects a state of the architecture, a power supp that generates power on the basis of vibration of the architecture, and a controller that controls the state detection sensor and the power supp. The controller supplies power to the state detection sensor to drive the state detection sensor in a case where a voltage by power generation exceeds a first threshold (threshold voltage), and acquires state information to be used for diagnosing the state of the architecture on the basis of a signal indicating a detection result received from the state detection sensor.
    Type: Application
    Filed: February 19, 2020
    Publication date: October 1, 2020
    Inventors: Junya TANAKA, Taichi NAKAMURA, Masanori MINAMIO, Daido KOMYOJI
  • Publication number: 20200108583
    Abstract: A heat insulating material includes an aerogel that has macro-pores and meso-pores. A method for manufacturing a heat insulating material, including: a sol preparation step of adding a gelling agent into sodium silicate such that a molar ratio of the gelling agent relative to NaO2 is 0.1 to 0.75, and adjusting a sol into which macro-pores are introduced by leaving unreacted Na and non-cross-linked oxygen in a siloxane skeleton; an impregnating and gelling step of impregnating a nonwoven fabric fiber structure with the sol to form a composite of hydrogel-nonwoven fabric fiber; a hydrophobizating step of mixing the formed composite of hydrogel-nonwoven fabric fiber with a silylating agent to modify a surface thereof; and a drying step of removing a liquid contained in the surface modified composite of hydrogel-nonwoven fabric fiber by drying under a temperature and pressure lower than respective critical values.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 9, 2020
    Inventors: KAZUMA OIKAWA, SHIGEAKI SAKATANI, KAZUHIRO NISHIKAWA, DAIDO KOMYOJI
  • Patent number: 9162249
    Abstract: A pin (125) is moved down in a nozzle (121), the end of paste (101) protruded from the discharge opening (122) of the nozzle (121) to a target object (102) is brought into contact with the target object (102), and the pin (125) is moved away from the discharge opening (122) to divide the paste in contact with the target object.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: October 20, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masayoshi Koyama, Norihito Tsukahara, Daido Komyoji
  • Patent number: 8866021
    Abstract: The invention includes: applying an anisotropic conductive resin including conductive particles only to a plurality of bumps of an electronic component; placing the electronic component above a main surface of a flexible wiring board via the anisotropic conductive resin; and pressurizing the electronic component to the wiring board and curing the anisotropic conductive resin applied to the plurality of bumps to join the plurality of bumps to the electrodes of the wiring board. This can prevent a defective mounting of the electronic component.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventors: Hidenobu Nishikawa, Daido Komyoji
  • Patent number: 8599571
    Abstract: Memory card (1) includes at least semiconductor chip (3), circuit board (2) with semiconductor chip (3) mounted on main surface (21), having at least rigidity reducing portion (23) formed in main surface (21) or in a linear region of surface (22) opposite to the main surface, and cover portion (71) for covering semiconductor chip (3) on main surface (21) of circuit board (2), wherein circuit board (2) has a plurality of convex regions (201) which flex in a convex shape toward main surface (21) due to rigidity reducing portion (23).
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: December 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Hidenobu Nishikawa, Daido Komyoji, Atsunobu Iwamoto, Hiroyuki Yamada, Shuichi Takeda, Shigeru Kondou
  • Publication number: 20130010436
    Abstract: The invention includes: applying an anisotropic conductive resin including conductive particles only to a plurality of bumps of an electronic component; placing the electronic component above a main surface of a flexible wiring board via the anisotropic conductive resin; and pressurizing the electronic component to the wiring board and curing the anisotropic conductive resin applied to the plurality of bumps to join the plurality of bumps to the electrodes of the wiring board. This can prevent a defective mounting of the electronic component.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 10, 2013
    Inventors: Hidenobu NISHIKAWA, Daido Komyoji
  • Patent number: 8291582
    Abstract: The invention includes: applying an anisotropic conductive resin including conductive particles only to a plurality of bumps of an electronic component; placing the electronic component above a main surface of a flexible wiring board via the anisotropic conductive resin; and pressurizing the electronic component to the wiring board and curing the anisotropic conductive resin applied to the plurality of bumps to join the plurality of bumps to the electrodes of the wiring board. This can prevent a defective mounting of the electronic component.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: October 23, 2012
    Assignee: Panasonic Corporation
    Inventors: Hidenobu Nishikawa, Daido Komyoji
  • Patent number: 8208270
    Abstract: Three-dimensional structure (40) of the present invention includes first module board (28), second module board (37), and substrate joining member (10) that unifies board (28) and board (37) into one body, thereby electrically connecting these two elements together. The unification is done by molding the outer wall of housing (12) of substrate joining member (10) with resin (29). Substrate joining member (10) used in the three-dimensional structure (40) includes multiple lead terminals (14) made of conductive material, and a frame-shaped and insulating housing (12) to which frame the lead terminals (14) are fixed vertically in a predetermined array. Housing (12) includes projections (18) on at least two outer wall faces of its frame shape.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: June 26, 2012
    Assignee: Panasonic Corporation
    Inventors: Masato Mori, Daido Komyoji, Koichi Nagai, Yoshihiko Yagi
  • Patent number: 8159829
    Abstract: Relay substrate (1) connecting between at least a first circuit board and a second circuit board, including housing (10) having recess (10a) provided in the outer circumference and hole (22) provided in the inner circumference; plural connecting terminal electrodes (12a, 12c) connecting between the top and bottom surfaces of housing (10); shield electrode (11) provided in recess (10a); and ground electrode (13) provided on a part of the top and bottom surfaces of housing (10).
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 17, 2012
    Assignee: Panasonic Corporation
    Inventors: Masato Mori, Daido Komyoji, Koichi Nagai, Yoshihiko Yagi
  • Patent number: 8125786
    Abstract: Memory card includes a circuit board, a component mounted on a main face of the circuit board, casing covering at least the main face of the circuit board and the component, and bittering agent retained in a roughened area provided on casing or an exposed part of the circuit board.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: February 28, 2012
    Assignee: Panasonic Corporation
    Inventors: Hidenobu Nishikawa, Daido Komyoji, Hiroyuki Yamada, Yutaka Nakamura, Shuichi Takeda, Yasuharu Kikuchi
  • Patent number: 8110933
    Abstract: A recess portion is formed on a board surface at a position facing a peripheral end portion of a semiconductor device so as to place a sealing-bonding resin partially inside the recess portion. Thereby, increases of a placement area for a fillet portion (foot spreading portion) of the sealing-bonding resin are suppressed while its inclination angle is increased. Thus, stress loads that occur to peripheral portions of the semiconductor device due to thermal expansion differences and thermal contraction differences among individual members caused by heating and cooling processes during a mounting operation are relaxed, by which internal breakdown of the semiconductor device mounted structure is avoided.
    Type: Grant
    Filed: December 25, 2007
    Date of Patent: February 7, 2012
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomura, Daido Komyoji
  • Patent number: 8058951
    Abstract: A configuration includes a first sheet substrate, on which a first thin film electronic component is formed on at least one main face, and an external connection terminal for connecting to an external circuit is formed one main face or the other face; a second sheet substrate, on which a second thin film electronic component is formed on at least one face; an insulator connection resin layer for fixing the first sheet substrate and the second sheet substrate opposing the first thin film electronic component against the second thin film electronic component; and an interlayer connection conductor for electrically connecting electrode terminals, which have been set in advance, of the first thin film electronic component and the second thin film electronic component.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: November 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Kenichi Yamamoto, Daido Komyoji, Keizaburo Kuramasu
  • Patent number: 7884443
    Abstract: A capacitor-equipped semiconductor device includes a semiconductor chip having a plurality of electrode terminals; a sheet-like substrate at least having a film capacitor; and a mounting substrate. The mounting substrate is provided on one side thereof with chip connection terminals and ground terminals. The chip connection terminals are disposed to correspond to the electrode terminals of the semiconductor chip. The ground terminals are disposed to correspond to the one electrode terminals of the film capacitor of the sheet-like substrate. The mounting substrate is provided on the other side thereof with external connection terminals connected to the chip connection terminals and the ground terminals and used to mount the mounting substrate on an external substrate.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: February 8, 2011
    Assignee: Panasonic Corporation
    Inventors: Kenichi Yamamoto, Daisuke Suetsugu, Daido Komyoji
  • Patent number: 7835160
    Abstract: First sheet-like substrate is arranged at a region surrounded by first terminals of male connector and first circuit substrate, and second sheet-like substrate is arranged at a region surrounded by second terminals of female connector and second circuit substrate, and male connector and female connector are fitted together so that a first passive element of first sheet-like substrate and a second passive element of second sheet-like substrate configure a filter circuit.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Kenichi Yamamoto, Daisuke Suetsugu, Daido Komyoji, Takashi Imanaka, Hirotaka Hisamura
  • Publication number: 20100148302
    Abstract: A capacitor-equipped semiconductor device includes a semiconductor chip having a plurality of electrode terminals; a sheet-like substrate at least having a film capacitor; and a mounting substrate. The mounting substrate is provided on one side thereof with chip connection terminals and ground terminals. The chip connection terminals are disposed to correspond to the electrode terminals of the semiconductor chip. The ground terminals are disposed to correspond to the one electrode terminals of the film capacitor of the sheet-like substrate. The mounting substrate is provided on the other side thereof with external connection terminals connected to the chip connection terminals and the ground terminals and used to mount the mounting substrate on an external substrate.
    Type: Application
    Filed: August 9, 2006
    Publication date: June 17, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Kenichi Yamamoto, Daisuke Suetsugu, Daido Komyoji
  • Publication number: 20100149777
    Abstract: First sheet-like substrate is arranged at a region surrounded by first terminals of male connector and first circuit substrate, and second sheet-like substrate is arranged at a region surrounded by second terminals of female connector and second circuit substrate, and male connector and female connector are fitted together so that a first passive element of first sheet-like substrate and a second passive element of second sheet-like substrate configure a filter circuit.
    Type: Application
    Filed: September 27, 2006
    Publication date: June 17, 2010
    Inventors: Kenichi Yamamoto, Daisuke Suetsugu, Daido Komyoji, Takashi Imanaka, Hirotaka Hisamura
  • Publication number: 20100090781
    Abstract: To provide a configuration including a first sheet substrate, on which a first thin film electronic component is formed on at least one main face, and an external connection terminal for connecting to an external circuit is formed one main face or the other face; a second sheet substrate, on which a second thin film electronic component is formed on at least one face; an insulator connection resin layer for fixing the first sheet substrate and the second sheet substrate opposing the first thin film electronic component against the second thin film electronic component; and an interlayer connection conductor for electrically connecting electrode terminals, which have been set in advance, of the first thin film electronic component and the second thin film electronic component.
    Type: Application
    Filed: September 22, 2006
    Publication date: April 15, 2010
    Inventors: Kenichi Yamamoto, Daido Komyoji, Keizaburo Kuramasu
  • Publication number: 20100084762
    Abstract: Memory card (1) includes at least semiconductor chip (3), circuit board (2) with semiconductor chip (3) mounted on main surface (21), having at least rigidity reducing portion (23) formed in main surface (21) or in a linear region of surface (22) opposite to the main surface, and cover portion (71) for covering semiconductor chip (3) on main surface (21) of circuit board (2), wherein circuit board (2) has a plurality of convex regions (201) which flex in a convex shape toward main surface (21) due to rigidity reducing portion (23).
    Type: Application
    Filed: April 18, 2007
    Publication date: April 8, 2010
    Inventors: Hidenobu Nishikawa, Daido Komyoji, Atsunobu Iwamoto, Hiroyuki Yamada, Shuichi Takeda, Shigeru Kondou