Patents by Inventor Daimotsu Kato

Daimotsu Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047534
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a first layer, a second layer, and a first insulating layer. The third electrode includes a first electrode portion. The first semiconductor region includes Alx1Ga1-x1N (0?x1<1). The first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region and a fifth partial region. The second semiconductor region includes Alx2Ga1-x2N (x1<x2?1). The second semiconductor region includes a first semiconductor portion and a second semiconductor portion. The first layer includes Al and N. The first layer includes a first compound region. The second layer includes Al, Si, O and N. The second layer includes a first intermediate region. The first insulating layer includes Si and O.
    Type: Application
    Filed: February 22, 2023
    Publication date: February 8, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke KAJIWARA, Hiroshi ONO, Daimotsu KATO, Aya SHINDOME, Masahiko KURAGUCHI
  • Patent number: 11757028
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: September 12, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Publication number: 20230268430
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1?x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1?x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1?x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Application
    Filed: April 26, 2023
    Publication date: August 24, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu KATO, Yosuke KAJIWARA, Akira MUKAI, Aya SHINDOME, Hiroshi ONO, Masahiko KURAGUCHI
  • Publication number: 20230253487
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, a first insulating member, and a nitride member. The third electrode includes a first electrode portion. A position of the first electrode portion is between a position of the first electrode and a position of the second electrode. The first semiconductor region includes first to fifth partial regions. A position of the fourth partial region is between positions of the first and third partial regions. A position of the fifth partial region is between positions of the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first electrode portion is located between the first and second semiconductor portions. The first insulating member includes first to third insulating regions. The nitride member includes first to third nitride regions.
    Type: Application
    Filed: August 5, 2022
    Publication date: August 10, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi ONO, Yosuke KAJIWARA, Daimotsu KATO, Masahiko KURAGUCHI, Tatsuo SHIMIZU
  • Patent number: 11677020
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1?x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1?x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1?x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 13, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu Kato, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
  • Publication number: 20230061811
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, first and second insulating members, a compound member, and a nitride member. The third electrode is between the first and second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes first and second insulating portions. The first semiconductor portion is between the fourth partial region and the first insulating portion. The second semiconductor portion is between the fifth partial region and the second insulating portion. The compound member includes first to third compound portions. The nitride member includes first to third nitride portions. The second insulating member includes first and second insulating regions.
    Type: Application
    Filed: March 1, 2022
    Publication date: March 2, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daimotsu KATO, Hiroshi ONO, Yosuke KAJIWARA, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI, Tatsuo SHIMIZU
  • Publication number: 20230068711
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first conductive member, first and second insulating members, and a first nitride member. A position of the third electrode in a first direction from the first to second electrodes is between positions of the first and second electrodes in the first direction. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first to fifth partial regions. The second semiconductor region includes first and second semiconductor portions. The second semiconductor portion includes first and second portions, and a third portion between the first and second portions. The first conductive member includes first and second conductive regions. The first insulating member includes a first insulating region. The second insulating member includes first and second insulating portions. The first nitride member includes a first nitride region.
    Type: Application
    Filed: March 1, 2022
    Publication date: March 2, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daimotsu KATO, Yosuke KAJIWARA, Hiroshi ONO, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI, Tatsuo SHIMIZU
  • Patent number: 11515411
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: November 29, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Patent number: 11476336
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, and a first compound member. A position of the third electrode is between a position of the second electrode and a position of the first electrode. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The fourth partial region is between the third and first partial regions. The fifth partial region is between the second and third partial regions. The second semiconductor layer includes first, second, and third semiconductor regions. The third semiconductor region is between the first partial region and the first electrode. The first compound member includes first compound portions between the third semiconductor region and the first electrode. A portion of the first electrode is between one of the first compound portions and an other one of the first compound portions.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 18, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Ono, Akira Mukai, Yosuke Kajiwara, Daimotsu Kato, Aya Shindome, Masahiko Kuraguchi
  • Publication number: 20220231155
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, first and second insulating members. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes a first insulating portion. The first insulating portion is between the third and first electrode portions. The second insulating member includes first and second insulating regions. The first insulating region is between the first electrode and the first electrode portion. The second insulating region is between the first insulating region and the first electrode portion.
    Type: Application
    Filed: August 10, 2021
    Publication date: July 21, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke KAJIWARA, Hiroshi ONO, Daimotsu KATO, Akira MUKAI, Masahiko KURAGUCHI
  • Publication number: 20220140125
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first semiconductor layer includes first, second, third, fourth, fifth, and sixth partial regions. The second semiconductor layer includes Alx2Ga1-x2N (0<x2—1, x1<x2). The second semiconductor layer includes first and second semiconductor portions. The first insulating member includes a first insulating region and includes a first material. The first insulating region contacts the third partial region and a part of the third electrode. The first member includes a first portion and includes a second material different from the first material. The first portion is between the fourth partial region and an other part of the third electrode.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daimotsu KATO, Hiroshi ONO, Tatsuo SHIMIZU, Yosuke KAJIWARA, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI
  • Publication number: 20220130986
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first member, and a first insulating member. The first semiconductor layer includes Alx1Ga1-x1N (0?x1<1). The first semiconductor layer includes first, second, third, fourth, fifth, and sixth partial regions. The second semiconductor layer includes Alx2Ga1-x2N (0<x2?1, x1<x2). The second semiconductor layer includes first and second semiconductor portions. The first insulating member includes a first insulating region and includes a first material. The first insulating region contacts the third partial region and a part of the third electrode. The first member includes a first portion and includes a second material different from the first material. The first portion is between the fourth partial region and an other part of the third electrode.
    Type: Application
    Filed: August 12, 2021
    Publication date: April 28, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daimotsu KATO, Hiroshi ONO, Tatsuo SHIMIZU, Yosuke KAJIWARA, Aya SHINDOME, Akira MUKAI, Po-Chin HUANG, Masahiko KURAGUCHI
  • Publication number: 20220115529
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Publication number: 20210384337
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1?x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1?x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1?x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Application
    Filed: August 20, 2021
    Publication date: December 9, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu KATO, Yosuke KAJIWARA, Akira MUKAI, Aya SHINDOME, Hiroshi ONO, Masahiko KURAGUCHI
  • Patent number: 11189718
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first conductive part, first and second insulating layers. The third electrode includes first and second portions. The first portion is between the first electrode and the second electrode. The first semiconductor layer includes first, second, third, fourth and fifth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor layer includes first and second semiconductor regions. The first conductive part is electrically connected to the first electrode. The first insulating layer includes a first insulating portion. The second insulating layer includes first and second insulating regions.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: November 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Patent number: 11139393
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes Alx1Ga1-x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1-x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1-x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: October 5, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu Kato, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
  • Patent number: 11088269
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a first insulating film. The first nitride region includes Alx1Ga1-x1N. The first nitride region includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second nitride region includes Alx2Ga1-x2N. The second nitride region includes sixth and seventh partial regions. The first insulating film includes a first insulating region and is between the third partial region and the third electrode. The third partial region has a first surface opposing the first insulating region. The fourth partial region has a second surface opposing the sixth partial region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: August 10, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu Kato, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
  • Publication number: 20210234032
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Application
    Filed: April 16, 2021
    Publication date: July 29, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Patent number: 11018248
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 25, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Patent number: 10964802
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira Mukai, Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi