Patents by Inventor Daisaburo Takashima

Daisaburo Takashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490271
    Abstract: According to one embodiment, a resistance change memory device comprises a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged, and a read unit to read the data of a selected one of the storage elements. In reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 26, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Patent number: 10468101
    Abstract: A semiconductor memory device comprises a memory cell including a resistance change memory element and a write control circuit for setting a resistance state of the resistance change memory element. The write control circuit applies a first voltage signal when setting the resistance change memory element. The first voltage signal rises in a first rise time from a first reference voltage to a first predetermined voltage, maintains at the first predetermined voltage for a first predetermined time period, and then falls from the first predetermined voltage to the first reference voltage in a first falling time. The write circuit applies a second or third voltage signal according to the state being set in the resistance change memory element. In some examples, a predetermined voltage level of the third signal is applied for a period of time longer than a predetermined level of the first and second voltage signals.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 5, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takahiko Iizuka, Daisaburo Takashima
  • Publication number: 20190295637
    Abstract: According to one embodiment, a memory device includes a first circuit including a resistance change memory element capable of setting a low resistance state or a high resistance state according to a falling speed of an applied voltage, and a first rectifier element connected in series to the resistance change memory element, and a second circuit including a current source, and a second rectifier element connected in series to the current source, the second circuit having a mirror relationship with the first circuit.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Publication number: 20190287615
    Abstract: A semiconductor memory device comprises a memory cell including a resistance change memory element and a write control circuit for setting a resistance state of the resistance change memory element. The write control circuit applies a first voltage signal when setting the resistance change memory element. The first voltage signal rises in a first rise time from a first reference voltage to a first predetermined voltage, maintains at the first predetermined voltage for a first predetermined time period, and then falls from the first predetermined voltage to the first reference voltage in a first falling time. The write circuit applies a second or third voltage signal according to the state being set in the resistance change memory element. In some examples, a predetermined voltage level of the third signal is applied for a period of time longer than a predetermined level of the first and second voltage signals.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 19, 2019
    Inventors: Takahiko IIZUKA, Daisaburo TAKASHIMA
  • Patent number: 10410720
    Abstract: A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takahiko Iizuka, Daisaburo Takashima, Ryu Ogiwara
  • Publication number: 20190088319
    Abstract: According to one embodiment, a resistance change memory device comprises a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged, and a read unit to read the data of a selected one of the storage elements. In reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element.
    Type: Application
    Filed: March 8, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Ryu OGIWARA, Daisaburo TAKASHIMA
  • Publication number: 20190088326
    Abstract: According to one embodiment, a nonvolatile memory device includes word lines, bit lines, resistance change memory elements, each selectively exhibiting a low or high-resistance state, and a write voltage generating circuit generating a write voltage supplied to the resistance change memory element selected via the bit line selected. The write voltage generating circuit supplies the write voltage to the first and second resistance change memory elements connected to one selected word line and two selected bit lines adjacent to each other in a temporally overlapping manner, and generates the write voltage such that a magnitude of the write voltage supplied to the first resistance change memory element becomes smaller when a write voltage for high-resistance state setting is supplied to the second resistance change memory element than when a write voltage for low-resistance state setting is supplied.
    Type: Application
    Filed: February 27, 2018
    Publication date: March 21, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Daisaburo TAKASHIMA
  • Patent number: 10236060
    Abstract: According to one embodiment, a nonvolatile memory device includes word lines, bit lines, resistance change memory elements, each selectively exhibiting a low or high-resistance state, and a write voltage generating circuit generating a write voltage supplied to the resistance change memory element selected via the bit line selected. The write voltage generating circuit supplies the write voltage to the first and second resistance change memory elements connected to one selected word line and two selected bit lines adjacent to each other in a temporally overlapping manner, and generates the write voltage such that a magnitude of the write voltage supplied to the first resistance change memory element becomes smaller when a write voltage for high-resistance state setting is supplied to the second resistance change memory element than when a write voltage for low-resistance state setting is supplied.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: March 19, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Daisaburo Takashima
  • Publication number: 20180277202
    Abstract: A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction.
    Type: Application
    Filed: September 4, 2017
    Publication date: September 27, 2018
    Inventors: Takahiko IIZUKA, Daisaburo TAKASHIMA, Ryu OGIWARA
  • Publication number: 20180268878
    Abstract: A variable resistance non-volatile semiconductor memory device comprises a memory cell having variable resistance element connected in series with a selection transistor. The selection transistor has a control terminal connected to a word line. A first end of the memory cell is connected to a bit line. A second end of the memory cell is connected to a first power supply line. An additional resistor is connected between a second power supply line and the bit line. The first power supply line is a low potential and the second power supply line is a high potential. During a reading operation of the memory cell, a read current flows through the first resistor and the memory cell.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 20, 2018
    Inventors: Ryu OGIWARA, Daisaburo TAKASHIMA
  • Patent number: 10032509
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first resistance element and a first transistor, a first bit line, a second transistor, and a sense circuit. The memory cell and the first circuit are connected to the first bit line. One end and the other end of the second transistor are connected to the first bit line and the sense circuit respectively. During a first operation before reading data of the memory cell a voltage of the first bit line falls to a first voltage and the first and second transistors are turned off in response to a fall of the voltage of the first bit line to the first voltage.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Patent number: 10014467
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: July 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Daisaburo Takashima
  • Patent number: 9966136
    Abstract: According to one embodiment, a variable resistance memory includes first to third insulating layers, first and second variable resistance layers, first and second semiconductor layers, and first and second electric conductors. The first insulating layer extends in a first direction. The first and second electric conductors are in contact with the second and third insulating layers respectively. The first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers are disposed between the first and second electric conductors in a second direction different from the first direction.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Patent number: 9928903
    Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell including a variable resistance element; a bit line coupled to the memory cell; and a first circuit applying a first voltage to the bit line in a write operation for the memory cell. When a temperature of the variable resistance element is lower than or equal to a first temperature, a temperature coefficient of the first voltage is 0. When the temperature of the variable resistance element is higher than the first temperature, the temperature coefficient of the first voltage is negative.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Publication number: 20180075903
    Abstract: According to one embodiment, a variable resistance memory includes first to third insulating layers, first and second variable resistance layers, first and second semiconductor layers, and first and second electric conductors. The first insulating layer extends in a first direction. The first and second electric conductors are in contact with the second and third insulating layers respectively. The first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers are disposed between the first and second electric conductors in a second direction different from the first direction.
    Type: Application
    Filed: February 27, 2017
    Publication date: March 15, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Ryu OGIWARA, Daisaburo TAKASHIMA
  • Publication number: 20170207272
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element.
    Type: Application
    Filed: April 4, 2017
    Publication date: July 20, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Daisaburo TAKASHIMA
  • Patent number: 9653681
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Daisaburo Takashima
  • Patent number: 9607693
    Abstract: A semiconductor storage device according to the present embodiments includes a first bit line and a first word line. A resistance-change memory element is connected to the first bit line and the first word line. A sense node is connected to the first bit line in a data read operation. A first transistor is connected between the sense node and the first bit line. A second transistor connects the first bit line and a power supply to each other in a data write operation. A first operational amplifier has one input connected to the first bit line, other input receiving a reference voltage, and an output connected in common to a gate of the first transistor and a gate of the second transistor. A sense circuit is connected to the sense node.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: March 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryu Ogiwara, Daisaburo Takashima
  • Publication number: 20160365143
    Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell including a variable resistance element; a bit line coupled to the memory cell; and a first circuit applying a first voltage to the bit line in a write operation for the memory cell. When a temperature of the variable resistance element is lower than or equal to a first temperature, a temperature coefficient of the first voltage is 0. When the temperature of the variable resistance element is higher than the first temperature, the temperature coefficient of the first voltage is negative.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryu OGIWARA, Daisaburo TAKASHIMA
  • Publication number: 20160293251
    Abstract: According to one embodiment, a semiconductor memory device includes: a plurality of memory cells, each of which including a memory element and a first switch element; the memory element storing data in accordance with a resistance values; a bit line connected to the memory cells; a charge transfer transistor that connects the bit line and a sense node; a sense circuit connected to the sense node; and a pulldown circuit connected to the bit line. The pulldown circuit causes a voltage of the bit line to drop to a first voltage obtained by subtracting a threshold voltage of the charge transfer transistor from a gate voltage of the charge transfer transistor before reading the data from the memory cell.
    Type: Application
    Filed: September 4, 2015
    Publication date: October 6, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryu OGIWARA, Daisaburo TAKASHIMA