Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell including a first two-terminal resistance change memory element storing memory cell information, and a second two-terminal resistance change memory element, connected in series to the first two-terminal resistance change memory element, and functioning as a selector element, word and bit lines connected to the memory cell. When memory cell information is to be written, if the memory cell is a selected memory cell, the second two-terminal resistance change memory element is set to the low resistance state and, if the memory cell is an unselected memory cell, the second two-terminal resistance change memory element is set to the high resistance state.

Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element and a selector element, a word line, a bit line connected to one end of the memory cell, an operational amplifier including a non-inverting input connected to the bit line, an output circuit including a first terminal connected to an output of the operational amplifier, a second terminal connected to the bit line, and a charge/discharge circuit including a capacitor, a charge circuit and a discharge circuit, each including one end connected to an inverting input of the operational amplifier. At the time of falling of a write voltage for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit.

Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell including a first two-terminal resistance change memory element storing memory cell information, and a second two-terminal resistance change memory element, connected in series to the first two-terminal resistance change memory element, and functioning as a selector element, word and bit lines connected to the memory cell. When memory cell information is to be written, if the memory cell is a selected memory cell, the second two-terminal resistance change memory element is set to the low resistance state and, if the memory cell is an unselected memory cell, the second two-terminal resistance change memory element is set to the high resistance state.

Abstract: According to one embodiment, a resistance change memory device comprises a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged, and a read unit to read the data of a selected one of the storage elements. In reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element.

Abstract: A semiconductor memory device comprises a memory cell including a resistance change memory element and a write control circuit for setting a resistance state of the resistance change memory element. The write control circuit applies a first voltage signal when setting the resistance change memory element. The first voltage signal rises in a first rise time from a first reference voltage to a first predetermined voltage, maintains at the first predetermined voltage for a first predetermined time period, and then falls from the first predetermined voltage to the first reference voltage in a first falling time. The write circuit applies a second or third voltage signal according to the state being set in the resistance change memory element. In some examples, a predetermined voltage level of the third signal is applied for a period of time longer than a predetermined level of the first and second voltage signals.

Abstract: According to one embodiment, a memory device includes a first circuit including a resistance change memory element capable of setting a low resistance state or a high resistance state according to a falling speed of an applied voltage, and a first rectifier element connected in series to the resistance change memory element, and a second circuit including a current source, and a second rectifier element connected in series to the current source, the second circuit having a mirror relationship with the first circuit.

Abstract: A semiconductor memory device comprises a memory cell including a resistance change memory element and a write control circuit for setting a resistance state of the resistance change memory element. The write control circuit applies a first voltage signal when setting the resistance change memory element. The first voltage signal rises in a first rise time from a first reference voltage to a first predetermined voltage, maintains at the first predetermined voltage for a first predetermined time period, and then falls from the first predetermined voltage to the first reference voltage in a first falling time. The write circuit applies a second or third voltage signal according to the state being set in the resistance change memory element. In some examples, a predetermined voltage level of the third signal is applied for a period of time longer than a predetermined level of the first and second voltage signals.

Abstract: A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction.

Abstract: According to one embodiment, a nonvolatile memory device includes word lines, bit lines, resistance change memory elements, each selectively exhibiting a low or high-resistance state, and a write voltage generating circuit generating a write voltage supplied to the resistance change memory element selected via the bit line selected. The write voltage generating circuit supplies the write voltage to the first and second resistance change memory elements connected to one selected word line and two selected bit lines adjacent to each other in a temporally overlapping manner, and generates the write voltage such that a magnitude of the write voltage supplied to the first resistance change memory element becomes smaller when a write voltage for high-resistance state setting is supplied to the second resistance change memory element than when a write voltage for low-resistance state setting is supplied.

Abstract: According to one embodiment, a resistance change memory device comprises a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged, and a read unit to read the data of a selected one of the storage elements. In reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element.

Abstract: According to one embodiment, a nonvolatile memory device includes word lines, bit lines, resistance change memory elements, each selectively exhibiting a low or high-resistance state, and a write voltage generating circuit generating a write voltage supplied to the resistance change memory element selected via the bit line selected. The write voltage generating circuit supplies the write voltage to the first and second resistance change memory elements connected to one selected word line and two selected bit lines adjacent to each other in a temporally overlapping manner, and generates the write voltage such that a magnitude of the write voltage supplied to the first resistance change memory element becomes smaller when a write voltage for high-resistance state setting is supplied to the second resistance change memory element than when a write voltage for low-resistance state setting is supplied.

Abstract: A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction.

Abstract: A variable resistance non-volatile semiconductor memory device comprises a memory cell having variable resistance element connected in series with a selection transistor. The selection transistor has a control terminal connected to a word line. A first end of the memory cell is connected to a bit line. A second end of the memory cell is connected to a first power supply line. An additional resistor is connected between a second power supply line and the bit line. The first power supply line is a low potential and the second power supply line is a high potential. During a reading operation of the memory cell, a read current flows through the first resistor and the memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first resistance element and a first transistor, a first bit line, a second transistor, and a sense circuit. The memory cell and the first circuit are connected to the first bit line. One end and the other end of the second transistor are connected to the first bit line and the sense circuit respectively. During a first operation before reading data of the memory cell a voltage of the first bit line falls to a first voltage and the first and second transistors are turned off in response to a fall of the voltage of the first bit line to the first voltage.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element.

Abstract: According to one embodiment, a variable resistance memory includes first to third insulating layers, first and second variable resistance layers, first and second semiconductor layers, and first and second electric conductors. The first insulating layer extends in a first direction. The first and second electric conductors are in contact with the second and third insulating layers respectively. The first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers are disposed between the first and second electric conductors in a second direction different from the first direction.

Abstract: According to one embodiment, a semiconductor storage device includes: a memory cell including a variable resistance element; a bit line coupled to the memory cell; and a first circuit applying a first voltage to the bit line in a write operation for the memory cell. When a temperature of the variable resistance element is lower than or equal to a first temperature, a temperature coefficient of the first voltage is 0. When the temperature of the variable resistance element is higher than the first temperature, the temperature coefficient of the first voltage is negative.

Abstract: According to one embodiment, a variable resistance memory includes first to third insulating layers, first and second variable resistance layers, first and second semiconductor layers, and first and second electric conductors. The first insulating layer extends in a first direction. The first and second electric conductors are in contact with the second and third insulating layers respectively. The first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers are disposed between the first and second electric conductors in a second direction different from the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first resistance-change memory elements of a two-terminal type, a second resistance-change memory element of a two-terminal type, a rectifier element of a two-terminal type, a local bit line connected to ends of the first resistance-change memory elements, an end of the second resistance-change memory element and an end of the rectifier element, and a global bit line connected to the other end of the second resistance-change memory element.

Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.