Abstract: A voltage generating circuit comprising: a switching device which includes a first end connected to a high potential side power source, and which becomes conductive in a first mode and becomes non-conductive in a second mode; a first transistor including a first main electrode connected to a second end of the switching device, a second main electrode connected to an output terminal, and a gate connected to a gate potential supply node; a second transistor including a first main electrode connected to the high potential side power source, a second main electrode connected to the output terminal, and a gate connected to the gate potential supply node; and a gate voltage stabilizing circuit that suppresses a fluctuation in potential of the potential supply node, the fluctuation accompanying a change between the first and second modes.

Abstract: A power supply circuit is disclosed. The power supply circuit is provided with a reference voltage generation circuit to receive a voltage from a higher voltage supply so as to generate a reference voltage. The reference voltage from the reference voltage generation circuit is outputted to a power supply voltage generation circuit. The power supply voltage generation circuit boosts the reference voltage to generate a boosted power supply voltage. The boosted power supply voltage is inputted to a bandgap reference circuit. The bandgap reference circuit generates a reference voltage by using the boosted power supply voltage.

Abstract: According to an aspect of the present invention, there is provided a power supply circuit including: a detection circuit that is connected to an external power supply voltage and that outputs a first signal indicating whether the external power supply voltage is in a dropped-state in which the external power supply voltage is dropped below a reference voltage; a control circuit that includes: a delay circuit that outputs a second signal acquired by delaying the first signal for a reference time; and a determination circuit that outputs a third signal based on the first signal and the second signal; a generation circuit that generates internal power supply voltage from the external power supply voltage and that supplies the internal power supply voltage; and an interruption circuit that interrupts the internal power supply voltage supplied from the generation circuit based on the third signal.

Abstract: An amplifying circuit receives an output from a comparator. The output is provided to each gate of first, second and third transistors. First and second resistors are connected in series. The first and second resistors and a first diode are connected to a drain of the first transistor. Second diodes are connected in parallel. The second diodes are connected to one end of a third resistor. The other end of the third resistor is connected to a drain of the second transistor. Fourth and fifth resistors are connected in series. One end of the fourth resistor is connected to the drain of the second transistor. The comparator receives first and second feedback voltages respectively obtained from a connection node between the first and second resistors and a connection node between the fourth and fifth resistors. A drain of the third transistor outputs a reference voltage.

Abstract: A first ferroelectric memory cell and a second ferroelectric memory cell each include a ferroelectric capacitor and a transistor and each store one set of information. A word-line is shared by the first and second ferroelectric memory cells. A first plate line is connected to the first ferroelectric memory cell and a second plate line is connected to the second ferroelectric memory cell. A selection transistor has one end connected to the first and second ferroelectric memory cells and the other end connected to a bit-line.

Abstract: According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first circuit configured to generate a first voltage that is independent of a power supply voltage and that is dependent of a temperature; a second circuit configured to generate a second voltage that is independent of the power supply voltage and that is dependent of the temperature; and a third circuit configured to compare the first voltage and the second voltage and to generate a reference voltage based on a higher one therebetween.

Abstract: A semiconductor memory device comprises a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor; a sense amp circuit operative to sense/amplify a signal read out of the ferroelectric capacitor through a pair of bit lines; a pair of decoupling transistors provided on the pair of bit lines to decouple the bit lines; a control circuit operative to provide a control signal to the gates of the decoupling transistors to control conduction of the decoupling transistors; and a dummy capacitor provided in connection with at least either one of the pair of bit lines between the decoupling transistors and the sense amp circuit. The control circuit is configured to be capable of turning the decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading.

Abstract: A ferroelectric memory includes a cell block that includes: a block select transistor arranged between a bit line and a local bit line; memory cells arranged between the local bit line and a plate line, each of the memory cells contains a cell transistor and a ferroelectric capacitor connected in series; and a reset transistor arranged between the local bit line and the plate line. A test method for the ferroelectric memory includes: applying a potential that allows the cell transistors to be ON to the word lines; applying a potential that allows the reset transistor to be OFF to the reset line; applying a potential that allows the block select transistor to be ON to the block select line; and applying a stress voltage between the bit line and the plate line.

Abstract: The sense amp circuit includes a first node given a first, positive constant voltage larger than a fixed potential before reading, a second node given a second, negative constant voltage smaller than the fixed potential before reading, and a third node to be connected to the first and second nodes on reading. A first transistor is connected between the first node and the bit line and operative to turn on when the potential on the bit line becomes smaller than the fixed potential. A second transistor is connected between the second node and the bit line and operative to turn on when the potential on the bit line becomes larger than the fixed potential. A first capacitor is connected between the first node and the fixed potential. A second capacitor is connected between the second node and the fixed potential.

Abstract: A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

Abstract: A first bit line is connected to a memory cell. A second bit line is connected to a dummy cell having a dummy capacitor, and supplied with an electric potential which is complementary to the electric potential of the first bit line. A sense amplifier compares and amplifies the first and second bit lines. A sense amplifier supply voltage generation circuit supplies the sense amplifier with a sense amplifier supply voltage to be used in the comparison and amplification by the sense amplifier. The sense amplifier supply voltage is supplied to a reference potential generation circuit. When data is read out from the memory cell to the first bit line, the reference potential generation circuit supplies, to the second bit line via the dummy cell, a reference potential which fluctuates with a positive correlation to the fluctuation in sense amplifier supply voltage.

Abstract: According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

Abstract: A power supply voltage control circuit supplying a power supply voltage to a memory cell array, including word lines extending along row direction, bit lines extending along column direction, plate lines extending along the row direction, and a plurality of unit cells disposed at intersections of word lines and bit lines, includes a word line control circuit for supplying a first voltage to the word lines; and a plate line control circuit for supplying a second voltage to the plate lines; and the power supply voltage control circuit provides an amount of current flow from the first voltage so as to keep the first voltage potential almost constant during increasing a value of the second voltage in a power-on sequence, firstly increasing a value of the higher voltage of two potential voltages: the first voltage and the second voltage capacitive coupled, and then increasing a value of the lower second voltage.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate and a plurality of cell transistors provided on a surface of the semiconductor substrate. A local bit line is provided above the cell transistors and electrically connected to one of a source diffusion layer and a drain diffusion layer of each of the cell transistors. Ferroelectric capacitors corresponding in number to the cell transistors, are provided above the local bit line, where each of the ferroelectric capacitors has an upper electrode and a lower electrode electrically connected to the other one of the source diffusion layer and drain diffusion layer of the corresponding one of the cell transistors. A plate line is provided above the upper electrodes and electrically connected to the upper electrodes. A reset transistor and a block selection transistor are provided on the surface of the semiconductor substrate.

Abstract: Four memory cells each obtained by connecting a ferroelectric capacitor in parallel to a transistor are connected in series with each other to constitute a cell block. A sense amplifier circuit is arranged on a one end side in a column direction every four cell blocks sequentially adjacent to each other in a row direction. One ends of the four cell blocks are connected to four different plate lines, respectively, and the other ends of the four cell blocks are connected to four different bit lines through four block selection transistors, respectively. Of the four bit lines, two bit lines constitute a first bit line pair, and the two remaining bit lines constitute a second bit line pair. Any one of the first and second bit line pairs is connected to the sense amplifier circuit and the other bit line pair is connected at a constant voltage.

Abstract: Disclosed is a voltage generating circuit which steps down a voltage to output a stepped down voltage. The voltage generating circuit includes first and second transistors. The drains of the first and second transistors are connected to a higher voltage power supply. The gate of the first transistor is connected to the gate of the second transistor. The voltage of the gate of the first transistor is controlled by a control circuit such that a voltage of the source of the first transistor can reach a predetermined voltage. A stepped down voltage is outputted from the source of the second transistor.

Abstract: A unit cell is formed by a ferroelectric capacitor and first MOS transistor, and a block is formed by connecting a plurality of unit cells in series. The gates of the first MOS transistors in the individual unit cells are connected to word lines, which are selectively driven by a word line driver on the basis of a row address signal. A plate line is connected to one terminal of the block, and driven by a plate line driver. A bit line is connected to the other terminal of the block via a second MOS transistor for block selection, and selected by a column decoder on the basis of a column address. A driver/controller controls the plate line driver and column decoder to apply a potential difference between the plate line and bit line, while a plurality of word lines are kept off.

Abstract: A memory system includes: a flash memory that stores data; a memory that stores a read count table that indicates the number of times of data read from the flash memory; and a controller that performs: reading out the data from the flash memory; updating the read count table when the controller performs reading out the data from the flash memory; and refreshing the flash memory based on the read count table.

Abstract: Disclosed is a semiconductor memory including ferroelectric capacitors. Memory cells each including a ferroelectric capacitor and an insulted-gate-type cell transistor are connected to a corresponding one of bit lines. Insulated-gate-type separating transistors are connected between multiple bit-line selecting transistors and multiple sense amplifiers, respectively. When the separating transistors are turned on, data retained in the sense amplifiers are capable of being written to the memory cells during the same time period substantially.

Abstract: According to an aspect of the present invention, there is provided a voltage generation circuit including: first and second reference terminals to output first and second reference voltages, respectively; first PMOS and first NMOS transistors connected between high and low level power supply lines in series; an output terminal connected between the first PMOS and first NMOS transistors; a first operational amplifier including: first input terminals each including a gate of a PMOS transistor to be connected to one of the second reference terminal and the output terminal, and a first output terminal connected to the first PMOS transistor; and a second operational amplifier including: second input terminals each including a gate of an NMOS transistor to be connected to one of the first reference terminal and the output terminal, and a second output terminal connected to the first NMOS transistor.