Abstract: According to one embodiment, a first node is connected to a gate of a second PMOS and a gate of a second NMOS, a second node is connected to a gate of a first PMOS and a gate of a first NMOS, a gate of the first transistor is connected to a first signal line, a source of a first transistor is connected to the first node, and a drain of the first transistor is connected to the second node, a gate of a second transistor is connected to the second node, a source of the second transistor is connected to a third node, and a drain of the second transistor is connected to a second signal line, and a gate of a third transistor is connected to a third signal line, a source of the third transistor is connected to a fourth signal line, and a drain of the third transistor is connected to the third node.

Abstract: A memory includes ferroelectric capacitors; cell transistors each including a drain connected to one electrode of each ferroelectric capacitor, and a gate connected to the word line; and memory cell blocks each including a reset transistor, a block selection transistor, and memory cells including the ferroelectric capacitors and the cell transistors, wherein sources of the cell transistors are connected to the plate lines, the other electrode of the ferroelectric capacitor is connected to one of the sub-bit lines, a source and a drain of the block selection transistor are connected to one of the sub-bit lines and one of the bit lines, a source of the reset transistor is connected to one of the plate lines or a fixed potential, and a drain of the reset transistor in each memory cell block is connected to one of the sub-bit lines, and the memory cell blocks configure a memory cell array.

Abstract: According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first transistor having a first gate, a first source and a first drain; a second transistor having a second gate connected to the first gate, a second source connected to the first source and a second drain; a first diode connected between a ground and a V? node; a first resistor connected between the V? node and the first drain; a second diode and a second resistor connected between the ground and a V+ node; a third resistor connected between the V+ node and the first drain; an operational amplifier including input ports connected to the V+ node and the V? node and an output port connected to the first gate and the second gate; and a fourth resistor connected between the ground and the second drain.

Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n?2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data.

Abstract: A memory includes ferroelectric capacitors; sense amplifiers configured to detect the data stored in ferroelectric capacitors; and a plate control circuit configured to receive a plate driving signal driving a plate line, a write signal indicating writing of data from an outside to the sense amplifier, and an operation end signal indicating end of an executable period for reading or writing data between the sense amplifier and the outside, the plate control circuit validating or invalidating the plate driving signal based on the write signal and the operation end signal wherein the plate control circuit validates the plate driving signal in the executable period, and the plate control circuit invalidates the plate driving signal at the end of the executable period when the write signal is never activated in the executable period, and keeps the plate driving signal valid when the write signal is activated in the executable period.

Abstract: The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric capacitor. A selection transistor selectively connects the memory cell to the bit line. A dummy cell provides a reference potential, the reference potential being referred to for a potential read from the memory cell. A sense amplifier circuit includes a plurality of amplification circuits amplifying the potential difference between a bit-line pair. A decoupling circuit electrically cuts off the bit line between the amplification circuits.

Abstract: An internal voltage generator according to an embodiment generates a reference voltage used for detecting data stored in a semiconductor memory. A first AD converter is configured to convert an external voltage supplied to the semiconductor memory into a first digital value. A second AD converter is configured to convert a temperature characteristic voltage that changes depending on a temperature of the semiconductor memory into a second digital value. An adder is configured to receive a reference voltage trimming address that specifies the reference voltage, the first digital value, and the second digital value, and to output a third digital value obtained by performing a weighted addition of the reference voltage trimming address, the first digital value, and the second digital value. A driver is configured to output the reference voltage responding to the third digital value.

Abstract: A memory system that can efficiently relieve a large number of defective bits with a small number of redundant bits is provided in a Flash-EEPROM nonvolatile memory. A memory system according to an embodiment of the present invention comprises a Flash-EEPROM memory in which a plurality of memory 5 having a floating gate or a charge trapping layer and capable of electrically erasing and writing data are arranged; a control circuit that controls a cache memory and the Flash-EEPROM memory; and an interface circuit that communicates with outside, wherein a plurality of group data and a plurality of flag data for storing presence of inversion of all bits of respective group data are stored in a memory area of the Flash-EEPROM memory.

Abstract: This disclosure concerns a memory system including: chips (MC00-MC37) laid out with erasure blocks, the erasure blocks respectively being formed by laying out with pages and being an erasure unit, the pages respectively being formed by laying out with cells; IO line groups connected to the chips, wherein the chips connected to the same IO line group form a memory group (MG0-MG3), and the memory group is divided into first to n-th sub-memory groups (BB-SGA to BB-SGD), and number of bad blocks of the chip having a smallest number of bad blocks in a k-th sub-memory group in the memory groups is larger than number of bad blocks of the chip having a largest number of the bad blocks in a (k+1)-th sub-memory group in the memory groups, the bad blocks are the erasure blocks in which erasing, writing or reading of data cannot be performed correctly.

Abstract: An amplifying circuit receives an output from a comparator. The output is provided to each gate of first, second and third transistors. First and second resistors are connected in series. The first and second resistors and a first diode are connected to a drain of the first transistor. Second diodes are connected in parallel. The second diodes are connected to one end of a third resistor. The other end of the third resistor is connected to a drain of the second transistor. Fourth and fifth resistors are connected in series. One end of the fourth resistor is connected to the drain of the second transistor. The comparator receives first and second feedback voltages respectively obtained from a connection node between the first and second resistors and a connection node between the fourth and fifth resistors. A drain of the third transistor outputs a reference voltage.

Abstract: According to an aspect of the present invention, there is provided a reference voltage generation circuit including: a first circuit configured to generate a first voltage that is independent of a power supply voltage and that is dependent of a temperature; a second circuit configured to generate a second voltage that is independent of the power supply voltage and that is dependent of the temperature; and a third circuit configured to compare the first voltage and the second voltage and to generate a reference voltage based on a higher one therebetween.

Abstract: A power supply circuit is disclosed. The power supply circuit is provided with a reference voltage generation circuit to receive a voltage from a higher voltage supply so as to generate a reference voltage. The reference voltage from the reference voltage generation circuit is outputted to a power supply voltage generation circuit. The power supply voltage generation circuit boosts the reference voltage to generate a boosted power supply voltage. The boosted power supply voltage is inputted to a bandgap reference circuit. The bandgap reference circuit generates a reference voltage by using the boosted power supply voltage.

Abstract: An internal power supply voltage generation circuit 100 has a first charge pump circuit which steps up the external power supply voltage in response to the first clock signal and outputs a first stepped up voltage from the first voltage stepup output terminal; a second charge pump circuit which steps up the first stepup voltage in response to the second clock signal and outputs a second stepped up voltage from the second voltage stepup output terminal, the second stepped up voltage being higher than the first stepped up voltage; a first voltage stepdown circuit which steps down the first stepped up voltage and outputs a first stepped down voltage; and a second voltage stepdown circuit which steps down the second stepped up voltage and outputs a second stepped down voltage, the second stepped down voltage being higher than the first stepped up voltage.

Abstract: Semiconductor memory contains memory cells having ferroelectric capacitors and cell transistors, bit lines connected to memory cells, word lines connected to gate electrodes of cell transistors, plate lines connected to one of two electrodes of ferroelectric capacitors, sense amplifiers connected between each pair of bit lines. Further, a test pad is provided in order to apply an external voltage to each of bit lines, test transistors are provided corresponding to bit lines respectively, each of test transistors is connected between the test pad and each of bit lines, a fatigue test bias circuit is connected to a first node located between the test pad and test transistors. Test transistors are shared in a first test to apply a first voltage to ferroelectric capacitors from an outside via the test pad and a second test to apply a second voltage to ferroelectric capacitors from the fatigue test bias circuit.

Abstract: A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being

Abstract: According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

Abstract: A semiconductor memory device includes a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor; a sense amp circuit operative to sense/amplify a signal read out of the ferroelectric capacitor through a pair of bit lines; a pair of decoupling transistors provided on the pair of bit lines to decouple the bit lines; a control circuit operative to provide a control signal to the gates of the decoupling transistors to control conduction of the decoupling transistors; and a dummy capacitor provided in connection with at least either one of the pair of bit lines between the decoupling transistors and the sense amp circuit. The control circuit is configured to be capable of turning the decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading.

Abstract: A memory system includes: a flash memory that stores data; a memory that stores a read count table that indicates the number of times of data read from the flash memory; and a controller that performs: reading out the data from the flash memory; updating the read count table when the controller performs reading out the data from the flash memory; and refreshing the flash memory based on the read count table.

Abstract: A voltage generating circuit comprising: a switching device which includes a first end connected to a high potential side power source, and which becomes conductive in a first mode and becomes non-conductive in a second mode; a first transistor including a first main electrode connected to a second end of the switching device, a second main electrode connected to an output terminal, and a gate connected to a gate potential supply node; a second transistor including a first main electrode connected to the high potential side power source, a second main electrode connected to the output terminal, and a gate connected to the gate potential supply node; and a gate voltage stabilizing circuit that suppresses a fluctuation in potential of the potential supply node, the fluctuation accompanying a change between the first and second modes.

Abstract: According to an aspect of the invention, there is provided, a semiconductor device, including an internal voltage generation circuit generating a prescribed voltage, a first test circuit connecting to a voltage-supplying wiring, one end of the voltage-supplying wiring being connected to a source wiring and the other end of the voltage-supplying wiring being connected to the internal voltage generation circuit, the first test circuit being supplied an outer voltage from the source wiring and a voltage of the internal voltage generation circuit through the voltage-supplying wiring, the first test circuit generating a prescribed resistance value on a basis of a control input from an outer portion in a test mode.