Abstract: A relay system includes a transmission device and a reception device. The transmission device includes: a first optical transmitter that converts a first signal to a first optical signal having a transmission speed equal to that of the first signal, and transmits the first optical signal; a data separator that converts the first signal to a plurality of low-rate signals having a lower speed than the first signal; a plurality of second optical transmitters each capable of converting the low-rate signals to low-rate optical signals and transmitting the optical signals, and converting a second signal to a second optical signal having a transmission speed equal to that of the second signal and transmitting the optical signal; and a multiplexer that multiplexes a plurality of optical signals selected from among the first optical signal, the low-rate optical signals, and the second optical signal, and outputs a multiplexed optical signal.

Abstract: A PON system according to one manner of the present invention includes an optical line terminal (OLT), at least one optical network unit (ONU), and an optical fiber that connects the optical line terminal and the optical network unit to each other. A reception level category for categorizing a reception level in the optical network unit, of an optical signal sent from the optical line terminal through the optical fiber is set. In discovery processing for searching for and registering an unregistered optical network unit, the optical line terminal registers an optical network unit corresponding to the reception level category.

Abstract: A PON system according to one manner of the present invention includes an optical line terminal (OLT), at least one optical network unit (ONU), and an optical fiber that connects the optical line terminal and the optical network unit to each other. A reception level category for categorizing a reception level in the optical network unit, of an optical signal sent from the optical line terminal through the optical fiber is set. In discovery processing for searching for and registering an unregistered optical network unit, the optical line terminal registers an optical network unit corresponding to the reception level category.

Abstract: A host board for mounting an optical transceiver includes a connector that is configured to attach thereto and detach therefrom an optical transceiver having at least one lane and includes electrical contacts as many as the at least one lane, a management unit configured to receive lane information regarding the at least one lane of the optical transceiver from the optical transceiver through the connector and specify an available electrical contact, and a communication unit configured to communicate with the optical transceiver through the connector. The communication unit is configured to communicate information with the optical transceiver through the electrical contact specified by the management unit.

Abstract: A pluggable optical module includes: a circuit board insertable to and removable from a connector of a host board; a plurality of first electrodes arranged in a first direction, which crosses an insert direction of the pluggable optical module, on a first surface of the circuit board; and a plurality of second electrodes arranged in the first direction on the first surface of the circuit board, the second electrodes being arranged on a host board side associated with the host board, with respect to the plurality of first electrodes. The first and second electrodes are arranged in accordance with a layout rule for tolerating electrical impact occurring when at least one of a plurality of terminals of the connector configured to be brought into contact with respective first electrodes of the plurality of first electrodes contacts any electrode of the plurality of second electrodes.

Abstract: An optical transceiver of the present disclosure includes: a first light emitting element configured to perform electric-optic conversion at a first transmission rate; a second light emitting element configured to perform electric-optic conversion at a second transmission rate higher than the first transmission rate; a light receiving element configured to perform optic-electric conversion at a predetermined transmission rate; an optical sub-assembly accommodating the light emitting elements and the light receiving element; a circuit board having a plurality of integrated circuits which are configured to drive the light emitting elements and the light receiving element; a housing accommodating the optical sub-assembly and the circuit board, the housing having a longest dimension in a longitudinal direction thereof and having thermal conductivity; a temperature sensor configured to detect a temperature inside the housing; a temperature control unit configured to determine a control value to be designated to th

Abstract: An optical transceiver of the present disclosure includes: a first light emitting element configured to perform electric-optic conversion at a first transmission rate; a second light emitting element configured to perform electric-optic conversion at a second transmission rate higher than the first transmission rate; a light receiving element configured to perform optic-electric conversion at a predetermined transmission rate; an optical sub-assembly accommodating the light emitting elements and the light receiving element; a circuit board having a plurality of integrated circuits which are configured to drive the light emitting elements and the light receiving element; a housing accommodating the optical sub-assembly and the circuit board, the housing having a longest dimension in a longitudinal direction thereof and having thermal conductivity; a temperature sensor configured to detect a temperature inside the housing; a temperature control unit configured to determine a control value to be designated to th

Abstract: A host board for mounting an optical transceiver includes a connector that is configured to attach thereto and detach therefrom an optical transceiver having at least one lane and includes electrical contacts as many as the at least one lane, a management unit configured to receive lane information regarding the at least one lane of the optical transceiver from the optical transceiver through the connector and specify an available electrical contact, and a communication unit configured to communicate with the optical transceiver through the connector. The communication unit is configured to communicate information with the optical transceiver through the electrical contact specified by the management unit.

Abstract: A configuration for receiving transmission data at multiple rates where one rate is not necessarily a multiple of another is provided. A host board includes a receiving circuit, a cross point switch, and a switch control circuit. The receiving circuit includes a receiving unit configured to receive a first data signal transmitted at a first rate, and a second receiving unit configured to receive a second data signal transmitted at a second rate different from the first rate. The cross point switch includes input terminals and output terminals. The cross point switch is configured to define a path of signal between the input terminals and the output terminals to route an input data signal to at least one of the first receiving unit and the second receiving unit.

Abstract: An object of the present invention is to provide a semiconductor device including a film to be processed having a uniform height. A first coating film made of photosensitive material is formed so as to cover step parts and to become thicker in a central part of a semiconductor substrate in planar view and to become thinner in an outer peripheral part. Next, a first pattern part located on the central part side relative to the step parts and a second pattern part located on the outer peripheral part side relative to the step parts are formed. The first pattern part and the second pattern part are formed so that the occupied area of the first pattern part in planar view becomes smaller than that of the second pattern part in planar view. Next, the first pattern part and the second pattern part are sagged by heating. Next, a second coating film is formed by spin coating so as to cover the step parts.

Abstract: An object of the present invention is to provide a semiconductor device including a film to be processed having a uniform height. A first coating film made of photosensitive material is formed so as to cover step parts and to become thicker in a central part of a semiconductor substrate in planar view and to become thinner in an outer peripheral part. Next, a first pattern part located on the central part side relative to the step parts and a second pattern part located on the outer peripheral part side relative to the step parts are formed. The first pattern part and the second pattern part are formed so that the occupied area of the first pattern part in planar view becomes smaller than that of the second pattern part in planar view. Next, the first pattern part and the second pattern part are sagged by heating. Next, a second coating film is formed by spin coating so as to cover the step parts.

Abstract: A configuration for receiving transmission data at multiple rates where one rate is not necessarily a multiple of another is provided. A host board includes a receiving circuit, a cross point switch, and a switch control circuit. The receiving circuit includes a receiving unit configured to receive a first data signal transmitted at a first rate, and a second receiving unit configured to receive a second data signal transmitted at a second rate different from the first rate. The cross point switch includes input terminals and output terminals. The cross point switch is configured to define a path of signal between the input terminals and the output terminals to route an input data signal to at least one of the first receiving unit and the second receiving unit.

Abstract: Provided is a method for manufacturing a semiconductor device including a film to be treated having a high flatness. A semiconductor substrate having a surface and including a first region and a second region on the surface is prepared, the first region being a region in which a plurality of first level difference portions are formed, the second region being a region in which a plurality of second level difference portions arranged more sparsely than the plurality of first level difference portions are formed, or a region in which no level difference portion is formed. A photosensitive film is formed on a portion of the second region to surround a periphery of the first region as seen in plan view. An applied film having flowability is formed to cover the first region and the photosensitive film. A portion of the applied film at least on the first region is removed.

Abstract: Provided is a method for manufacturing a semiconductor device including a film to be treated having a high flatness. A semiconductor substrate having a surface and including a first region and a second region on the surface is prepared, the first region being a region in which a plurality of first level difference portions are formed, the second region being a region in which a plurality of second level difference portions arranged more sparsely than the plurality of first level difference portions are formed, or a region in which no level difference portion is formed. A photosensitive film is formed on a portion of the second region to surround a periphery of the first region as seen in plan view. An applied film having flowability is formed to cover the first region and the photosensitive film. A portion of the applied film at least on the first region is removed.

Abstract: The present invention relates to a receiving apparatus 20 that receives burst signals, each including a synchronization section and a data section following the synchronization section, from a plurality of sources in a time division manner. The receiving apparatus 20 includes amplifying units 102 and 113 that amplify each burst signal; a detecting unit 116 that detects arrival of the burst signal from an output signal from the amplifying units 102 and 113; a comparing unit 104 that compares the output signal from the amplifying units 102 and 113 with a predetermined threshold value and outputs a binary signal; and a control unit 108 that sets the timings of changing a receive function during the synchronization section by adding delay times Dai and Dbi to a detection time point where the detecting unit 116 performs an output. The control unit 108 is configured to be able to change the delay times Dai and Dbi in a plurality of ways.

Abstract: The present invention relates to a receiving apparatus 20 that receives burst signals, each including a synchronization section and a data section following the synchronization section, from a plurality of sources in a time division manner. The receiving apparatus 20 includes amplifying units 102 and 113 that amplify each burst signal; a detecting unit 116 that detects arrival of the burst signal from an output signal from the amplifying units 102 and 113; a comparing unit 104 that compares the output signal from the amplifying units 102 and 113 with a predetermined threshold value and outputs a binary signal; and a control unit 108 that sets the timings of changing a receive function during the synchronization section by adding delay times Dai and Dbi to a detection time point where the detecting unit 116 performs an output. The control unit 108 is configured to be able to change the delay times Dai and Dbi in a plurality of ways.

Abstract: An integrated circuit according to one embodiment includes a first transimpedance amplifier and a second transimpedance amplifier. In the integrated circuit, one of the first transimpedance amplifier and the second transimpedance amplifier is set into an enabled state and the other is set into a disabled state. The first transimpedance amplifier and the second transimpedance amplifier share an input transistor. The first transimpedance amplifier has a first resistor provided between a feedback node thereof and an input node connected to the input transistor. The second transimpedance amplifier has a second resistor provided between a feedback node thereof and the first resistor. A feedback resistor of the second transimpedance amplifier is configured with a series connection of the first resistor and the second resistor.

Abstract: An amplifier includes a first transistor having a first conducting electrode receiving a current, a control electrode coupled to the first conducting electrode, and a second conducting electrode coupled to a fixed voltage source; a second transistor having a first conducting electrode, a second conducting electrode and a control electrode coupled to the control electrode of the first transistor; a feedback resistance coupled to the control electrode of the second transistor for feeding back an output of the second transistor to the control electrode of the second transistor; and a variable resistance element for controlling a ratio between a current flowing from the first conducting electrode of the first transistor into the control electrode of the second transistor and the feedback resistance and a current flowing from the first conducting electrode into the second conducting electrode in the first transistor.

Abstract: An integrated circuit according to one embodiment includes a first transimpedance amplifier and a second transimpedance amplifier. In the integrated circuit, one of the first transimpedance amplifier and the second transimpedance amplifier is set into an enabled state and the other is set into a disabled state. The first transimpedance amplifier and the second transimpedance amplifier share an input transistor. The first transimpedance amplifier has a first resistor provided between a feedback node thereof and an input node connected to the input transistor. The second transimpedance amplifier has a second resistor provided between a feedback node thereof and the first resistor. A feedback resistor of the second transimpedance amplifier is configured with a series connection of the first resistor and the second resistor.

Abstract: An amplifier includes a first transistor having a first conducting electrode receiving a current, a control electrode coupled to the first conducting electrode, and a second conducting electrode coupled to a fixed voltage source; a second transistor having a first conducting electrode, a second conducting electrode and a control electrode coupled to the control electrode of the first transistor; a feedback resistance coupled to the control electrode of the second transistor for feeding back an output of the second transistor to the control electrode of the second transistor; and a variable resistance element for controlling a ratio between a current flowing from the first conducting electrode of the first transistor into the control electrode of the second transistor and the feedback resistance and a current flowing from the first conducting electrode into the second conducting electrode in the first transistor.