Abstract: A method for forming a hole plug in a laminate structure is provided. A laminate structure, is formed, including at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. An unpierced or blind hole is formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the hole having a hole depth to hole diameter aspect ratio of less than twenty (20) to one (1). In yet another example, the hole aspect ratio may be less than one (1) to one (1). Via fill ink may then be deposited in the hole. The via fill ink is then dried and/or cured to form a hole plug.

Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.

Abstract: Novel methods for forming a printed circuit board (PCB) having one or more segmented vias are provided, including improved methods of removing the catalyst after the plating process when forming a segmented via in the PCB. After the electroless plating, excess catalyst on the surface of the plating resist is removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating is then applied to the through holes and the outer layer circuit or signal traces are formed. That is, the etching of paths on the conductive foils/layers of the core structure.

Abstract: A core or sub-composite structure is provided including a dielectric layer between a first conductive film and a second conductive film. The first conductive film may include a first peelable/removable cover layer formed on or coupled to a first conductive layer. The second conductive film may include a second peelable/removable cover layer formed on or coupled to a second conductive layer.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.